PIC18F452-I/PG Microchip Technology, PIC18F452-I/PG Datasheet - Page 245
![IC MCU FLASH 16KX16 W/AD 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F452-I/PG
Manufacturer Part Number
PIC18F452-I/PG
Description
IC MCU FLASH 16KX16 W/AD 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18F452-I/PG
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
For Use With
ACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- Current page: 245 of 332
- Download datasheet (6Mb)
RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2006 Microchip Technology Inc.
Q Cycle Activity:
After Interrupt
operation
Decode
PC = TOS
No
Q1
operation
operation
Return from Subroutine
[ label ]
s
(TOS)
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ‘s’= 1, the contents of the
shadow registers WS, STATUSS
and BSRS are loaded into their cor-
responding registers, W, STATUS
and BSR. If ‘s’ = 0, no update of
these registers occurs (default).
1
2
RETURN
0000
No
No
Q2
[0,1]
W,
PC,
RETURN [s]
BSR,
0000
operation
Process
Data
No
STATUS,
Q3
0001
pop PC from
operation
stack
No
Q4
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
C
REG
W
C
Q1
=
=
=
=
=
register 'f'
Rotate Left f through Carry
[ label ]
0
d
a
(f<n>)
(f<7>)
(C)
C, N, Z
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0, the result
is placed in W. If 'd' is 1, the result
is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
RLCF
Read
Q2
0011
1110 0110
0
1110 0110
1100 1100
1
f
[0,1]
[0,1]
PIC18FXX2
C
dest<0>
255
dest<n+1>,
C,
RLCF
01da
Process
REG, 0, 0
Data
Q3
register f
DS39564C-page 243
f [,d [,a]
ffff
destination
Write to
Q4
ffff
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