DSPIC30F3011-30I/P Microchip Technology, DSPIC30F3011-30I/P Datasheet - Page 15
![IC DSPIC MCU/DSP 24K 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
DSPIC30F3011-30I/P
Manufacturer Part Number
DSPIC30F3011-30I/P
Description
IC DSPIC MCU/DSP 24K 40DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20IP.pdf
(26 pages)
2.DSPIC30F3010-30ISO.pdf
(228 pages)
3.DSPIC30F3010-30ISO.pdf
(18 pages)
4.DSPIC30F3010-30ISO.pdf
(6 pages)
5.DSPIC30F3010-30ISO.pdf
(16 pages)
6.DSPIC30F3010-30ISO.pdf
(22 pages)
7.DSPIC30F3010-20ISP.pdf
(226 pages)
Specifications of DSPIC30F3011-30I/P
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
24KB (8K x 24)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Core Frequency
40MHz
Core Supply Voltage
5.5V
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
30
Flash Memory Size
24KB
Supply Voltage Range
2.5V To 5.5V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC30F003 - MODULE SOCKET DSPIC30F 40DIPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F3011-30IP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F3011-30I/P
Manufacturer:
Microchip
Quantity:
927
Company:
Part Number:
DSPIC30F3011-30I/PT
Manufacturer:
MICROCHIP
Quantity:
316
Company:
Part Number:
DSPIC30F3011-30I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
DSPIC30F3011-30I/PT
Manufacturer:
MICROCHI
Quantity:
20 000
25. Module: I
26. Module: I
© 2008 Microchip Technology Inc.
In 10-bit Addressing mode, some address
matches don't set the RBF flag or load the receive
register I2CxRCV, if the lower address byte
matches the reserved addresses. In particular,
these include all addresses with the form
XX0000XXXX
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
When the I
slave with and address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01
rather
acknowledges both address bytes.
Work around
None.
than
2
2
2
C
C
C module is configured as a 10-bit
0x02;
and
XX1111XXXX,
however,
the
with
module
the
27. Module: I
Note:
dsPIC30F3010/3011
When the I
I2CEN bit in the I2CCON register, the dsPIC DSC
device generates a glitch on the SDA and SCL
pins. This glitch falsely indicates “Communication
Start” to all devices on the I
a bus collision in a multi-master configuration.
Additionally, when the I2CEN bit is set, the S and
P bits of the I
‘0’, respectively, which indicate a “Communication
Start” condition.
Work arounds
To avoid this issue, either of the following two work
arounds can be implemented, depending on the
application requirements.
Work around 1:
In a single-master environment, add a delay
between enabling the I
transmission. The delay should be equal to or
greater than the time it takes to transmit two data
bits.
In the multi-master configuration, in addition to the
delay, all other I
nized and wait for the I
before initiating any kind of communication.
Work around 2:
In dsPIC DSC devices in which the I
multiplexed
precedence in the use of the pin, it is possible to
avoid this glitch by enabling the higher priority
module before enabling the I
Use the following procedure to implement this
work around:
1. Enable the higher priority peripheral module
2. Set up and enable the I
Disable the higher priority peripheral module that
was enabled in step 1.
that is multiplexed on the same pins as the I
module.
Work around 2 works only for devices that
share the SDA and SCL pins with another
peripheral that has a higher precedence
over the port latch, such as the UART. The
priority is shown in the pin diagram located
in the data sheet. For example, if the SDA
and SCL pins are shared with the UART
and SPI pins, and the UART has higher
precedence on the port latch pin.
2
2
C
C module is enabled by setting the
2
with
C module are set to values ‘1’ and
2
C masters should be synchro-
other
2
2
C module and the first data
C module to be initialized
2
2
modules
C bus, and can cause
C module.
2
C module.
DS80216K-page 15
2
C module is
that
have
2
C