DSPIC30F3011-30I/P Microchip Technology, DSPIC30F3011-30I/P Datasheet - Page 13

• Manufacturer Part Number: DSPIC30F3011-30I/P
• Description: IC DSPIC MCU/DSP 24K 40DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3011-30I/P

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 30
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F003 - MODULE SOCKET DSPIC30F 40DIPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLEACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F3011-30IP

35.3.2.2.2 SPITBF Status Flag Operation
Figure 35-4:
© 2008 Microchip Technology Inc.
Note 1: Operation for 8-bit mode is shown; the 16-bit mode is similar.
SCK1 Input
(CKP = 0
CKE = 0)
SCK1 Input
(CKP = 1
CKE = 0)
SDO1
Output
SDI1 Input
(SMP = 0)
Input
Sample
(SMP = 0)
SPITBF
SPIRBF
SPI1IF
2: Two SPI1 Clock modes are shown only to demonstrate CKP (SPI1CON1<6>) and CKE (SPI1CON1<8>) bit
3: If there are no pending transmissions or a transmission is in progress, SPI1BUF is transferred to SPI1SR as soon
(2)
(2)
functionality. Any combination of CKP and CKE bits can be selected for module operation.
as the user application writes to SPI1BUF.
User application
writes to
SPI1BUF
SPI1 Slave Mode Timing (Slave Select Pin Disabled)
Section 35. Serial Peripheral Interface (SPI) (Part II)
The SPITBF (SPI1STAT<1>) bit functions differently in the Slave mode of operation than in
Master mode.
If SSEN (SPI1CON1<7>) is cleared, the SPITBF is set when the SPI1BUF is loaded by the user
application. It is cleared when the module transfers SPI1TXB to SPI1SR. This is similar to the
SPITBF bit function in Master mode.
If SSEN is set, the SPITBF is set when the SPI1BUF is loaded by the user application. However,
it is cleared only when the SPI1 module completes data transmission. A transmission will be
aborted when the SS1 pin goes high, but may be retried at a later time. Each data word is held
in SPI1TXB until all bits are transmitted to the receiver.
(3)
bit 7
bit 7
bit 6
bit 5
bit 4
1 instruction cycle latency to set
SPI1IF flag bit
bit 3
(1)
bit 2
SPI1SR to
SPI1RXB
bit 1
bit 0
DS70272B-page 35-13
bit 0
35