PIC18F442-I/PTG Microchip Technology, PIC18F442-I/PTG Datasheet - Page 102
PIC18F442-I/PTG
Manufacturer Part Number
PIC18F442-I/PTG
Description
IC PIC MCU FLASH 8KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18F442-I/PTG
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- Current page: 102 of 332
- Download datasheet (6Mb)
PIC18FXX2
9.6
The Parallel Slave Port is implemented on the 40-pin
devices only (PIC18F4X2).
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit, PSPMODE
(TRISE<4>) is set. It is asynchronously readable and
writable by the external world through RD control input
pin, RE0/RD and WR control input pin, RE1/WR.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D port config-
uration bits PCFG2:PCFG0 (ADCON1<2:0>) must be
set, which will configure pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>)
is set. In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs), and the ADCON1 is configured for digital I/O.
In this mode, the input buffers are TTL.
FIGURE 9-11:
DS39564C-page 100
PORTD<7:0>
PSPIF
Parallel Slave Port
OBF
CS
WR
RD
IBF
Q1
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q2
Q3
Q4
Q1
Q2
FIGURE 9-10:
One bit of PORTD
Note: I/O pin has protection diodes to V
Data Bus
Q3
Set Interrupt Flag
PSPIF (PIR1<7>)
WR LATD
or
PORTD
RD PORTD
RD LATD
Q4
TRIS Latch
Data Latch
Q
D
C K
Q1
EN
EN
Q
D
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
© 2006 Microchip Technology Inc.
Q2
Chip Select
Read
Write
Q3
TTL
DD
TTL
TTL
TTL
and V
Q4
SS
RDx
Pin
CS
WR
.
RD
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