PIC16C774/PT Microchip Technology, PIC16C774/PT Datasheet - Page 37
PIC16C774/PT
Manufacturer Part Number
PIC16C774/PT
Description
IC MCU OTP 4KX14 A/D PWM 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C773SO.pdf
(201 pages)
3.PIC16C774P.pdf
(13 pages)
4.PIC16C774P.pdf
(16 pages)
Specifications of PIC16C774/PT
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
7KB (4K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C774/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16C773SO PDF datasheet #2
- PIC16C774P PDF datasheet #3
- PIC16C774P PDF datasheet #4
- Current page: 37 of 201
- Download datasheet (3Mb)
3.6
The Parallel Slave Port is implemented on the
40/44-pin devices only.
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The configuration
bits, PCFG3:PCFG0 (ADCON1<3:0>) must be config-
ured to make pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
FIGURE 3-14: PARALLEL SLAVE PORT WRITE WAVEFORMS
PORTD<7:0>
1999 Microchip Technology Inc.
PSPIF
Parallel Slave Port
OBF
CS
WR
RD
IBF
Q1
Q2
Q3
Advance Information
Q4
Q1
Q2
FIGURE 3-13: PORTD AND PORTE BLOCK
One bit of PORTD
Note: I/O pin has protection diodes to V
Data bus
Set interrupt flag
PSPIF (PIR1<7>)
Q3
WR
PORT
RD
PORT
Q4
Q
D
CK
DIAGRAM (PARALLEL SLAVE
PORT)
EN
Q1
EN
Q
D
PIC16C77X
Q2
Chip Select
Read
Write
Q3
DS30275A-page 37
TTL
DD
TTL
TTL
TTL
and V
Q4
SS
CS
WR
RD
RDx
pin
.
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