DSPIC33FJ64GS610-E/PT Microchip Technology, DSPIC33FJ64GS610-E/PT Datasheet - Page 121

• Manufacturer Part Number: DSPIC33FJ64GS610-E/PT
• Description: MCU/DSP 16BIT 64KB FLASH 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ64GS610-E/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (64K x 8)
• Package / Case: 100-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 9K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Numeric And Arithmetic Format: Fixed-Point or Floating-Point
• Instruction Set Architecture: Harvard
• Device Million Instructions Per Second: 40 MIPs
• Maximum Clock Frequency: 120 MHz
• Number Of Programmable I/os: 85
• Data Ram Size: 4 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• On-chip Dac: 10 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.9
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the Reset.
TABLE 6-2:
 2010 Microchip Technology Inc.
TRAPR (RCON<15>)
IOPWR (RCON<14>)
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
Note:
dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Note:
Flag Bit
Using the RCON Status Bits
All Reset flag bits can be set or cleared by user software.
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
RESET FLAG BIT OPERATION
Trap conflict event
Illegal opcode or uninitialized W register
access or Security Reset
MCLR Reset
RESET instruction
WDT time-out
PWRSAV #SLEEP instruction
PWRSAV #IDLE instruction
POR, BOR
POR
Set by:
Preliminary
Table 6-2 provides a summary of the Reset flag bit
operation.
POR,BOR
POR,BOR
POR
POR,BOR
PWRSAV instruction, CLRWDT instruction,
POR,BOR
POR,BOR
POR,BOR
Cleared by:
DS70591C-page 121