PIC16F876-10E/SP Microchip Technology, PIC16F876-10E/SP Datasheet - Page 68
![IC MCU FLASH 8KX14 EE 28DIP](/photos/6/59/65908/150-28-dip_sml.jpg)
PIC16F876-10E/SP
Manufacturer Part Number
PIC16F876-10E/SP
Description
IC MCU FLASH 8KX14 EE 28DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873-04SO.pdf
(218 pages)
5.PIC16F873-04SO.pdf
(5 pages)
6.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F876-10E/SP
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16F87610E/SP
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- PIC16F873-04SO PDF datasheet #6
- Current page: 68 of 218
- Download datasheet (4Mb)
PIC16F87X
REGISTER 9-1:
DS30292C-page 66
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)
bit 7
SMP : Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in slave mode
In I
1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for high speed mode (400 kHz)
CKE: SPI Clock Edge Select (Figure 9-2, Figure 9-3 and Figure 9-4)
SPI mode:
For CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
For CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
In I
1 = Input levels conform to SMBus spec
0 = Input levels conform to I
D/A: Data/Address bit (I
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: STOP bit
(I
1 = Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET)
0 = STOP bit was not detected last
S: START bit
(I
1 = Indicates that a START bit has been detected last (this bit is ’0’ on RESET)
0 = START bit was not detected last
R/W: Read/Write bit Information (I
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next START bit, STOP bit or not ACK bit.
In I
1 = Read
0 = Write
In I
1 = Transmit is in progress
0 = Transmit is not in progress
Logical OR of this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode.
UA: Update Address (10-bit I
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
Receive (SPI and I
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I
1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
- n = Value at POR
2
2
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
R/W-0
2
2
2
2
SMP
C Master or Slave mode:
C Master or Slave mode:
C Slave mode:
C Master mode:
2
C mode only):
R/W-0
CKE
2
C modes):
2
C mode only)
W = Writable bit
’1’ = Bit is set
2
C specs
2
C mode only)
R-0
D/A
2
C mode only)
R-0
P
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R-0
S
R/W
R-0
2001 Microchip Technology Inc.
x = Bit is unknown
R-0
UA
R-0
BF
bit 0
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