PIC18F442-E/P Microchip Technology, PIC18F442-E/P Datasheet - Page 161
![IC MCU CMOS 40MHZ 8K FLASH 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F442-E/P
Manufacturer Part Number
PIC18F442-E/P
Description
IC MCU CMOS 40MHZ 8K FLASH 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18F442-E/P
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
34
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F442-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- Current page: 161 of 332
- Download datasheet (6Mb)
15.4.14
While in SLEEP mode, the I
addresses or data, and when an address match or
complete byte transfer occurs, wake the processor
from SLEEP (if the MSSP interrupt is enabled).
15.4.15
A RESET disables the MSSP module and terminates
the current transfer.
15.4.16
In Multi-Master mode, the interrupt generation on the
detection of the START and STOP conditions allows the
determination of when the bus is free. The STOP (P)
and START (S) bits are cleared from a RESET or when
the MSSP module is disabled. Control of the I
may be taken when the P bit (SSPSTAT<4>) is set, or
the bus is idle with both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate the
interrupt when the STOP condition occurs.
In multi-master operation, the SDA line must be moni-
tored for arbitration, to see if the signal level is the
expected output level. This check is performed in
hardware, with the result placed in the BCLIF bit.
The states where arbitration can be lost are:
• Address Transfer
• Data Transfer
• A START Condition
• A Repeated START Condition
• An Acknowledge Condition
FIGURE 15-25:
© 2006 Microchip Technology Inc.
SDA
SCL
BCLIF
SLEEP OPERATION
EFFECT OF A RESET
MULTI-MASTER MODE
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
Data changes
while SCL = 0
2
C module can receive
2
C bus
SDA released
by master
SDA line pulled low
by another source
15.4.17
Multi-Master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, arbitration takes place when the master
outputs a '1' on SDA, by letting SDA float high and
another master asserts a '0'. When the SCL pin floats
high, data should be stable. If the expected data on
SDA is a '1' and the data sampled on the SDA pin = '0',
then a bus collision has taken place. The master will set
the Bus Collision Interrupt Flag BCLIF and reset the I
port to its IDLE state (Figure 15-25).
If a transmit was in progress when the bus collision
occurred, the transmission is halted, the BF flag is
cleared, the SDA and SCL lines are de-asserted, and
the SSPBUF can be written to. When the user services
the bus collision Interrupt Service Routine, and if the
I
asserting a START condition.
If a START, Repeated START, STOP, or Acknowledge
condition was in progress when the bus collision
occurred, the condition is aborted, the SDA and SCL
lines are de-asserted, and the respective control bits in
the SSPCON2 register are cleared. When the user ser-
vices the bus collision Interrupt Service Routine, and if
the I
by asserting a START condition.
The master will continue to monitor the SDA and SCL
pins. If a STOP condition occurs, the SSPIF bit will be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the
transmitter left off when the bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is IDLE and the S and P bits are
cleared.
2
C bus is free, the user can resume communication by
2
C bus is free, the user can resume communication
MULTI -MASTER COMMUNICATION,
BUS COLLISION, AND BUS
ARBITRATION
Sample SDA. While SCL is high,
data doesn’t match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt (BCLIF)
PIC18FXX2
DS39564C-page 159
2
2
C
C
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