PIC18F442-E/P Microchip Technology, PIC18F442-E/P Datasheet - Page 63
![IC MCU CMOS 40MHZ 8K FLASH 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F442-E/P
Manufacturer Part Number
PIC18F442-E/P
Description
IC MCU CMOS 40MHZ 8K FLASH 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F242-ISO.pdf
(332 pages)
3.PIC18F242-ISO.pdf
(14 pages)
4.PIC18F242-ISO.pdf
(16 pages)
5.PIC18F242-ISO.pdf
(16 pages)
6.PIC18F242-ISO.pdf
(14 pages)
7.PIC18LF242-ISO.pdf
(36 pages)
Specifications of PIC18F442-E/P
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
34
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LDACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F442-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F242-ISO PDF datasheet #2
- PIC18F242-ISO PDF datasheet #3
- PIC18F242-ISO PDF datasheet #4
- PIC18F242-ISO PDF datasheet #5
- PIC18F242-ISO PDF datasheet #6
- PIC18LF242-ISO PDF datasheet #7
- Current page: 63 of 332
- Download datasheet (6Mb)
5.5
The minimum programming block is 4 words or 8 bytes.
Word or byte programming is not supported.
Table Writes are used internally to load the holding reg-
isters needed to program the FLASH memory. There
are 8 holding registers used by the Table Writes for
programming.
Since the Table Latch (TABLAT) is only a single byte,
the TBLWT instruction has to be executed 8 times for
each programming operation. All of the Table Write
FIGURE 5-5:
5.5.1
The sequence of events for programming an internal
program memory location should be:
1.
2.
3.
4.
5.
6.
7.
8.
9.
© 2006 Microchip Technology Inc.
TBLPTR = xxxxx0
Read 64 bytes into RAM.
Update data values in RAM as necessary.
Load Table Pointer with address being erased.
Do the row erase procedure.
Load Table Pointer with address of first byte
being written.
Write the first 8 bytes into the holding registers
with auto-increment (TBLWT*+ or TBLWT+*).
Set EEPGD bit to point to program memory,
clear the CFGS bit to access program memory,
and set WREN to enable byte writes.
Disable interrupts.
Write 55h to EECON2.
Writing to FLASH Program
Memory
FLASH PROGRAM MEMORY WRITE
SEQUENCE
Holding Register
8
TABLE WRITES TO FLASH PROGRAM MEMORY
TBLPTR = xxxxx1
Holding Register
8
Program Memory
TBLPTR = xxxxx2
Write Register
TABLAT
operations will essentially be short writes, because only
the holding registers are written. At the end of updating
8 registers, the EECON1 register must be written to, to
start the programming operation with a long write.
The long write is necessary for programming the inter-
nal FLASH. Instruction execution is halted while in a
long write cycle. The long write will be terminated by
the internal programming timer.
The EEPROM on-chip timer controls the write time.
The write/erase voltages are generated by an on-chip
charge pump rated to operate over the voltage range of
the device for byte or word operations.
10. Write AAh to EECON2.
11. Set the WR bit. This will begin the write cycle.
12. The CPU will stall for duration of the write (about
13. Re-enable interrupts.
14. Repeat steps 6-14 seven times, to write
15. Verify the memory (Table Read).
This procedure will require about 18 ms to update one
row of 64 bytes of memory. An example of the required
code is given in Example 5-3.
Note:
Holding Register
2 ms using internal timer).
64 bytes.
8
Before setting the WR bit, the table pointer
address needs to be within the intended
address range of the 8 bytes in the holding
registers.
TBLPTR = xxxxx7
PIC18FXX2
Holding Register
DS39564C-page 61
8
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