DSPIC33FJ256GP710A-E/PF Microchip Technology, DSPIC33FJ256GP710A-E/PF Datasheet - Page 309
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DSPIC33FJ256GP710A-E/PF
Manufacturer Part Number
DSPIC33FJ256GP710A-E/PF
Description
IC DSPIC DSC 256K FLASH 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ64GP206-IPT.pdf
(322 pages)
2.DSPIC33FJ64GP206A-IMR.pdf
(338 pages)
3.DSPIC33FJ128GP306A-IPT.pdf
(350 pages)
Specifications of DSPIC33FJ256GP710A-E/PF
Program Memory Type
FLASH
Program Memory Size
256KB (256K x 8)
Package / Case
100-TQFP
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
85
Ram Size
30K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 32x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
85
Data Ram Size
30 KB
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM300019, DV164033, MA330011, MA330012, DM300024
Minimum Operating Temperature
- 40 C
Package
100TQFP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
64-chx10-bit|64-chx12-bit
Number Of Timers
9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC33FJ256GP710A-E/PF
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
DSPIC33FJ256GP710A-E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC33FJ64GP206-IPT PDF datasheet
- DSPIC33FJ64GP206A-IMR PDF datasheet #2
- DSPIC33FJ128GP306A-IPT PDF datasheet #3
- Current page: 309 of 322
- Download datasheet (5Mb)
APPENDIX A:
Revision A (October 2006)
Initial release of this document.
Revision B (March 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
The major changes are referenced by their respective
section in the following table.
TABLE A-1:
© 2009 Microchip Technology Inc.
Section 1.0 “Device Overview”
Section 3.0 “Memory Organization”
Section 5.0 “Reset”
Section 7.0 “Direct Memory Access (DMA)” Updated the table cross-reference in Note 2 in the DMAxREQ
Section Name
MAJOR SECTION UPDATES
REVISION HISTORY
dsPIC33FJXXXGPX06/X08/X10
Added External Interrupt pin information (INT0 through INT4) to
Table 1-1.
Updated Change Notification Register Map table title to reflect
application with dsPIC33FJXXXMCX10 devices (Table 3-2).
Added Change Notification Register Map tables (Table 3-3 and
Table 3-4) for dsPIC33FJXXXMCX08 and dsPIC33FJXXXMCX06
devices, respectively.
Updated the bit range for AD1CON3 (ADCS<7:0>) in the ADC1
Register Map and added Note 1 (Table 3-15).
Updated the bit range for AD2CON3 (ADCS<7:0>) in the ADC2
Register Map (Table 3-16).
Updated the Reset value for C1FEN1 (FFFF) in the ECAN1 Register
Map When C1CTRL1.WIN = 0 or 1 (Table 3-18) and updated the
title to reflect applicable devices.
Updated the title in the ECAN1 Register Map When C1CTRL1.WIN
= 0 to reflect applicable devices (Table 3-19).
Updated the title in the ECAN1 Register Map When C1CTRL1.WIN
= 1 to reflect applicable devices (Table 3-20).
Updated the Reset value for C2FEN1 (FFFF) in the ECAN2 Register
Map When C2CTRL1.WIN = 0 or 1 (Table 3-21) and updated the
title to reflect applicable devices.
Updated the title for the ECAN2 Register Map When C2CTRL1.WIN
= 0 to reflect applicable devices (Table 3-22).
Updated the title for the ECAN2 Register Map When C2CTRL1.WIN
= 1 to reflect applicable devices (Table 3-23).
Updated Reset value for TRISA (C6FF) and changed the bit 12 and
bit 13 values for ODCA to unimplemented in the PORTA Register
Map (Table 3-25).
Changed the bit 10 and bit 9 values for PMD1 to unimplemented in
the PMD Register Map (Table 3-34).
Added POR and BOR references in Reset Flag Bit Operation
(Table 5-1).
register (Register 7-2).
Update Description
DS70286C-page 307
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