DSPIC30F2023-30I/ML Microchip Technology, DSPIC30F2023-30I/ML Datasheet - Page 10
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DSPIC30F2023-30I/ML
Manufacturer Part Number
DSPIC30F2023-30I/ML
Description
IC DSPIC MCU/DSP 12K 44QFN
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F2023-30I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
30 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Core Frequency
30MHz
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
35
Flash Memory Size
12KB
Supply Voltage Range
3V To 5.5V
Operating Temperature Range
-40°C To +85°C
Package
44QFN EP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
30 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
35
Interface Type
I2C/SPI/UART
On-chip Adc
12-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DSPIC30F2023-30I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
dsPIC30F Family Reference Manual
35.3.2.1.1 External Clocking in Master Mode
DS70272B-page 35-10
To set up the SPI1 module for the Master mode of operation, perform the following steps:
1.
2.
3.
4.
5.
Example 35-1 shows a code snippet for configuring the SPI register for the Master mode.
Example 35-1:
In Master mode, the module can also be configured to operate with an external data clock. SPI1
clock operation is controlled by the DISSCK bit (SPI1CON1<12>). When this bit is set, the
internal data clock is disabled and data is transferred when external clock pulses are presented
on the SCK1 pin. All other aspects of Master mode operation are the same as described above.
/* Following code snippet shows SPI register configuration for MASTER mode*/
IFS0bits.SPI1IF = 0;
IEC0bits.SPI1IE = 0;
SPI1CON1bits.DISSCK = 0;
SPI1CON1bits.DISSDO = 0;
SPI1CON1bits.MODE16 = 1;
SPI1CON1bits.SMP = 0;
SPI1CON1bits.CKE = 0;
SPI1CON1bits.CKP = 0;
SPI1CON1bits.MSTEN = 1;
SPI1STATbits.SPIEN = 1;
SPI1BUF = 0x0000;
IFS0bits.SPI1IF = 0;
IEC0bits.SPI1IE = 1;
Note:
If using interrupts:
a)
b)
c)
Write the desired settings to the SPI1CON1 register with MSTEN (SPI1CON1<5>) = 1.
Clear the SPIROV bit (SPI1STAT<6>).
Enable SPI1 module operation by setting the SPIEN bit (SPI1STAT<15>).
Write the data to be transmitted to the SPI1BUF register. Transmission (and reception) will
start as soon as data is written to the SPI1BUF register.
Clear the SPI1IF bit in the IFS0 register.
Set the SPI1IE bit in the IEC0 register.
Write the SPI1IP bits in the IPC2 register to set the interrupt priority.
The DISSCK bit is available only in SPI Master modes.
SPI Configuration – Master Mode
//Clear the Interrupt Flag
//disable the Interrupt
//SPI1CON1 Register Settings
//Internal Serial Clock is Enabled.
//SDO1 pin is controlled by the module.
//Communication is word-wide (16 bits).
//Input Data is sampled at the middle of data
//output time.
//Serial output data changes on transition from
//Idle clock state to active clock state
//Idle state for clock is a low level; active
//state is a high level
//Master Mode Enabled
//Enable SPI Module
//Write data to be transmitted
//Interrupt Controller Settings
//Clear the Interrupt Flag
//Enable the Interrupt
© 2008 Microchip Technology Inc.