PIC18F6525T-I/PT Microchip Technology, PIC18F6525T-I/PT Datasheet - Page 20
![IC PIC MCU FLASH 24KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6525T-I/PT
Manufacturer Part Number
PIC18F6525T-I/PT
Description
IC PIC MCU FLASH 24KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6525-IPT.pdf
(396 pages)
3.PIC18F6525-IPT.pdf
(8 pages)
4.PIC18F6525-IPT.pdf
(38 pages)
Specifications of PIC18F6525T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6525T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6X2X/8X2X
3.5
The Boot Block segment is programmed in exactly the
same manner as the ID locations (see Section 3.4).
Multi-panel writes must be disabled so that only
addresses in the range 0000h to 07FFh will be written.
The code sequence detailed in Table 3-7 should be
used, except that the address data used in “Step 2” will
be in the range 000000h to 0007FFh.
TABLE 3-8:
DS30499B-page 20
Step 1: Direct access to config memory.
Step 2: Position the program counter
Step 3
Step 4: Execute four NOPs.
Note 1:
Command
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1111
0000
0000
1111
0000
0000
0000
0000
0000
4-bit
(2)
2:
: Set Table Pointer for config byte to be written. Write even/odd addresses.
Boot Block Programming
If the code protection bits are programmed while the program counter resides in the same block, then the interaction of
code protection logic may prevent further table write. To avoid this situation, move the program counter outside the
code protection area (e.g., GOTO 100000h).
Enabling the write protection of configuration bits (WRTC = 0 in CONFIG6H) will prevent further writing of configuration
bits. Always write all the configuration bits before enabling the write protection for configuration bits.
8E A6
8C A6
EF 00
F8 00
0E 30
6E F8
0E 00
6E F7
0E 00
6E F6
<LSB><MSB ignored>
00 00
2A F6
<LSB ignored><MSB>
00 00
00 00
00 00
00 00
00 00
SET ADDRESS POINTER TO CONFIGURATION LOCATION
Data Payload
(1)
.
BSF
BSF
GOTO
MOVLW 30h
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPRTH
MOVLW 00h
MOVWF TBLPTRL
Load 2 bytes and start programming
NOP - hold PGC high for time P9
INCF
Load 2 bytes and start programming
NOP - hold PGC high for time P9
EECON1, EEPGD
EECON1, CFGS
100000h
TBLPTRL
Programming” 4-bit command (1111) is used, but only
3.6
Unlike code memory, the configuration bits are pro-
grammed a byte at a time. The “Table Write, Begin
8 bits of the following 16-bit payload will be written. The
LSB of the payload will be written to even addresses and
the MSB will be written to odd addresses. The code
sequence to program two consecutive configuration
locations is shown in Table 3-8.
Note:
Core Instruction
Configuration Bits Programming
Execute
configuration byte programming.
four
2003 Microchip Technology Inc.
NOPs
between
every