PIC18F4539-I/P Microchip Technology, PIC18F4539-I/P Datasheet - Page 210
![IC MCU FLASH 12KX16 EE A/D 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4539-I/P
Manufacturer Part Number
PIC18F4539-I/P
Description
IC MCU FLASH 12KX16 EE A/D 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2439-ISO.pdf
(322 pages)
3.PIC18F2439-ISO.pdf
(6 pages)
Specifications of PIC18F4539-I/P
Core Size
8-Bit
Program Memory Size
24KB (12K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1408 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
32
Eeprom Memory Size
256Byte
Ram Memory Size
1.375KB
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
24 KB
Interface Type
I2C, SPI, AUSART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F4539-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F4539-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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- Download datasheet (7Mb)
PIC18FXX39
20.4.1
The user memory may be read to, or written from, any
location using the Table Read and Table Write instruc-
tions. The device ID may be read with Table Reads.
The configuration registers may be read and written
with the Table Read and Table Write instructions.
In User mode, the CPn bits have no direct effect. CPn
bits inhibit external reads and writes. A block of user
memory may be protected from Table Writes if the
WRTn configuration bit is ‘0’. The EBTRn bits control
Table Reads. For a block of user memory with the
EBTRn bit set to ‘0’, a Table Read instruction that exe-
cutes from within that block is allowed to read. A Table
FIGURE 20-4:
DS30485A-page 208
TBLPTR = 000FFF
Register Values
Results: All Table Writes disabled to Blockn whenever WRTn = 0
PC = 001FFE
PC = 004FFE
PROGRAM MEMORY
CODE PROTECTION
TABLE WRITE (WRTn) DISALLOWED
Program Memory
Preliminary
TBLWT *
TBLWT *
Read instruction that executes from a location outside
of that block is not allowed to read, and will result in
reading ‘0’s. Figures 20-4 through 20-6 illustrate Table
Write and Table Read protection.
Note:
000000h
0001FFh
005FFFh
000200h
001FFFh
002000h
003FFFh
004000h
.
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code pro-
tection bits are only set to ‘1’ by a block
erase function. The block erase function
can only be initiated via ICSP or an
external programmer.
Configuration Bit Settings
WRTB,EBTRB = 11
WRT0,EBTR0 = 01
WRT1,EBTR1 = 11
WRT2,EBTR2 = 11
2002 Microchip Technology Inc.
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