PIC24FJ128DA206-I/PT Microchip Technology, PIC24FJ128DA206-I/PT Datasheet - Page 74
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PIC24FJ128DA206-I/PT
Manufacturer Part Number
PIC24FJ128DA206-I/PT
Description
MCU PIC 16BIT FLASH 128K 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Specifications of PIC24FJ128DA206-I/PT
Core Size
16-Bit
Program Memory Size
128KB (43K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC24
No. Of I/o's
52
Ram Memory Size
96KB
Cpu Speed
32MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
96 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
29
Number Of Timers
5
Operating Supply Voltage
2.2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240312, DV164039
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ128DA206-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC24FJ256DA210 FAMILY
The page registers (DSRPAG/DSWPAG) do not
update automatically while crossing a page boundary,
when the rollover happens from 0xFFFF to 0x8000.
While developing code in assembly, care must be taken
to update the page registers when an Address Pointer
crosses the page boundary. The ‘C’ compiler keeps
track of the addressing, and increments or decrements
the page registers accordingly while accessing
contiguous data memory locations.
TABLE 4-35:
DS39969B-page 74
Note 1:
(Data Space Read Register)
2:
3:
4:
DSRPAG
If the source/destination address is below 0x8000, the DSRPAG and DSWPAG registers are not considered.
This data space can also be accessed by Direct Addressing.
When the source/destination address is above 0x8000 and DSRPAG/DSWPAG is ‘0’, an address error
trap will occur.
EPMP memory space can start from location, 0x008000, in the parts with 24 Kbytes of data memory
(PIC24FJXXXDA1XX)
0x1FF
0x001
0x002
0x003
0x004
0x000
x
(1)
•
•
•
EDS MEMORY ADDRESS WITH DIFFERENT PAGES AND ADDRESSES
(Data Space Write
DSWPAG
Register)
0x1FF
0x001
0x002
0x003
0x004
0x000
x
(1)
•
•
•
Indirect Addressing
Source/Destination
0x8000 to 0xFFFF
0x0000 to 0x1FFF
0x2000 to 0x7FFF
Address while
Note 1: All write operations to EDS are executed
2: Use of Read/Modify/Write operation on
3: Use
in a single cycle.
any EDS location under a REPEAT
instruction is not supported. For example,
BCLR, BSW, BTG, RLC f, RLNC f,
RRC f, RRNC f, ADD f, SUB f,
SUBR f, AND f, IOR f, XOR f,
ASR f, ASL f.
performing Read/Modify/Write operation.
the
Invalid Address Address error
0xFF8000 to
0x000000 to
0x002000 to
0x008000 to
0x010000 to
0x018000 to
0x018800 to
Pointing to
0xFFFFFE
0x00FFFE
0x017FFE
0x027FFE
2010 Microchip Technology Inc.
0x001FFF
0x007FFF
0x0187FE
24-Bit EA
DSRPAG
EDS
•
•
•
register
Near data
space
32 Kbytes on
each page
Only 2 Kbytes
of extended
SRAM on this
page
EPMP
memory
space
trap
Comment
(3)
(2)
(4)
while
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