PIC24FJ128DA206-I/PT Microchip Technology, PIC24FJ128DA206-I/PT Datasheet - Page 91
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PIC24FJ128DA206-I/PT
Manufacturer Part Number
PIC24FJ128DA206-I/PT
Description
MCU PIC 16BIT FLASH 128K 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Specifications of PIC24FJ128DA206-I/PT
Core Size
16-Bit
Program Memory Size
128KB (43K x 24)
Core Processor
PIC
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, GFX, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Controller Family/series
PIC24
No. Of I/o's
52
Ram Memory Size
96KB
Cpu Speed
32MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
96 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
29
Number Of Timers
5
Operating Supply Voltage
2.2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, AC164127-4, AC164127-6, AC164139, DM240312, DV164039
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ128DA206-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- Current page: 91 of 408
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TABLE 6-3:
6.3.1
The oscillator start-up circuitry and its associated delay
timers are not linked to the device Reset delays that
occur at power-up. Some crystal circuits (especially
low-frequency crystals) will have a relatively long
start-up time. Therefore, one or more of the following
conditions is possible after SYSRST is released:
• The oscillator circuit has not begun to oscillate.
• The Oscillator Start-up Timer has not expired (if a
• The PLL has not achieved a lock (if PLL is used).
The device will not begin to execute code until a valid
clock source has been released to the system. There-
fore, the oscillator and PLL start-up delays must be
considered when the Reset delay time must be known.
2010 Microchip Technology Inc.
POR
BOR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
crystal oscillator is used).
Reset Type
(7)
2:
3:
4:
5:
6:
7:
T
T
WUTSEL<1:0> bits setting).
T
T
oscillator clock to the system.
T
T
If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC
so the system clock delay is just T
primary oscillator after its respective clock delay.
POR AND LONG OSCILLATOR
START-UP TIMES
STARTUP
OST
RST
POR
LOCK
FRC
= Internal State Reset time (32 s nominal).
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
and T
= Power-on Reset delay (10 s nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time.
EC
ECPLL
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
LPRC
EC
ECPLL
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
LPRC
Any Clock
Any Clock
Any clock
Any Clock
Any Clock
Any Clock
= T
LPRC
VREG
Clock Source
= RC Oscillator start-up times.
(10 s nominal when VREGS = 1 and when VREGS = 0; depends upon
FRC
PIC24FJ256DA210 FAMILY
, and in such cases, FRC start-up time is valid. It switches to the
T
T
T
T
T
T
T
POR
POR
POR
POR
POR
POR
POR
T
T
T
T
T
T
T
SYSRST Delay
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
+ T
+ T
+ T
+ T
+ T
+ T
+ T
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
6.3.2
If the FSCM is enabled, it will begin to monitor the
system clock source when SYSRST is released. If a
valid clock source is not available at this time, the
device will automatically switch to the FRC oscillator
and the user can switch to the desired crystal oscillator
in the Trap Service Routine (TSR).
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
+ T
+ T
+ T
RST
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
+ T
+ T
+ T
RST
RST
RST
RST
RST
RST
RST
FAIL-SAFE CLOCK MONITOR
(FSCM) AND DEVICE RESETS
System Clock
T
T
T
T
OST
OST
FRC
FRC
T
T
Delay
T
T
T
T
T
T
LOCK
LPRC
LOCK
LPRC
OST
+ T
OST
+ T
FRC
+ T
FRC
+ T
—
—
—
—
—
—
—
—
LOCK
LOCK
LOCK
LOCK
DS39969B-page 91
1, 2, 3
1, 2, 3, 5
1, 2, 3, 4
1, 2, 3, 4, 5
1, 2, 3, 6, 7
1, 2, 3, 5, 6
1, 2, 3, 6
2, 3
2, 3, 5
2, 3, 4
2, 3, 4, 5
2, 3, 6, 7
2, 3, 5, 6
2, 3, 6
3
3
3
3
3
3
Notes
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