PIC18F4685-E/P Microchip Technology, PIC18F4685-E/P Datasheet - Page 40
PIC18F4685-E/P
Manufacturer Part Number
PIC18F4685-E/P
Description
IC PIC MCU FLASH 48KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PCM18XT0.pdf
(484 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F2682-ISP.pdf
(6 pages)
4.PIC18F2682-ISP.pdf
(4 pages)
Specifications of PIC18F4685-E/P
Program Memory Type
FLASH
Program Memory Size
96KB (48K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
44
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4680 - BOARD DAUGHTER ICEPIC3DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
PIC18F4685-E/P
Manufacturer:
MICROCHIP
Quantity:
2 000
Company:
Part Number:
PIC18F4685-E/P
Manufacturer:
Microchip Technology
Quantity:
135
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PIC18F4685-E/P
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PIC18F4685-E/PT
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MICROCHIP
Quantity:
2 000
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PIC18F4685-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4685-E/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PCM18XT0 PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2682-ISP PDF datasheet #3
- PIC18F2682-ISP PDF datasheet #4
- Current page: 40 of 484
- Download datasheet (9Mb)
PIC18F2682/2685/4682/4685
3.4.1
This mode is unique among the three low-power Idle
modes in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP
instruction. If the device is in another Run mode, set
IDLEN first, then clear the SCS bits and execute
SLEEP. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified by the FOSC3:FOSC0 Configuration bits.
The OSTS bit remains set (see Figure 3-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval T
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 3-8).
FIGURE 3-7:
FIGURE 3-8:
DS39761C-page 40
CPU Clock
Peripheral
Program
Counter
CPU Clock
Peripheral
OSC1
Clock
Program
Counter
OSC1
PRI_IDLE MODE
Clock
Q1
Q1
TRANSITION TIMING FOR ENTRY TO IDLE MODE
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q2
Wake Event
PC
Q3
T
CSD
Q4
CSD
Q1
is
PC
executing code being clocked by the Timer1 oscillator.
3.4.2
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS1:SCS0 bits to ‘01’ and execute
SLEEP. When the clock source is switched to the
Timer1 oscillator, the primary oscillator is shut down,
the OSTS bit is cleared and the T1RUN bit is set.
When a wake event occurs, the peripherals continue
to be clocked from the Timer1 oscillator. After an inter-
val of T
The IDLEN and SCS bits are not affected by the
wake-up; the Timer1 oscillator continues to run (see
Figure 3-8).
Note:
CSD
SEC_IDLE MODE
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled but not yet run-
ning, peripheral clocks will be delayed until
the oscillator has started. In such situations,
initial oscillator operation is far from stable
and unpredictable operation may result.
PC + 2
following the wake event, the CPU begins
Q2
© 2009 Microchip Technology Inc.
Q3
Q4
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