ATSAM3S1BA-MU Atmel, ATSAM3S1BA-MU Datasheet - Page 49

• Manufacturer Part Number: ATSAM3S1BA-MU
• Description: IC MCU 32BIT 64KB FLASH 64QFN
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-MU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.7
6500CS–ATARM–24-Jan-11
Pulse Width Modulation Controller (PWM)
• Each channel is user-configurable and contains:
• Two global registers that act on all three TC Channels
• Quadrature decoder
• 2-bit Gray Up/Down Counter for Stepper Motor
• One Four-channel 16-bit PWM Controller, 16-bit counter per channel
• Common clock generator, providing Thirteen Different Clocks
• Independent channel programming
• Synchronous Channel mode
• Connection to one PDC channel
• independent event lines which can send up to 4 triggers on ADC within a period
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
– Advanced line filtering
– Position / revolution / speed
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– High Frequency Asynchronous clocking mode
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Independent Output Override for each channel
– Independent complementary Outputs with 12-bit dead time generator for each
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Synchronous Channels share the same counter
– Mode to update the synchronous channels registers after a programmable number
– Offers Buffer transfer without Processor Intervention, to update duty cycle of
channel
of periods
synchronous channels
SAM3S Summary
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