PIC18F8722-E/PT Microchip Technology, PIC18F8722-E/PT Datasheet

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PIC18F8722-E/PT

Manufacturer Part Number
PIC18F8722-E/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F8722-E/PT

Core Size
8-Bit
Program Memory Size
128KB (64K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Controller Family/series
PIC18
No. Of I/o's
70
Eeprom Memory Size
1024Byte
Ram Memory Size
3936Byte
Cpu Speed
40MHz
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164136 - DEVELOPMENT KIT FOR PIC18XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F8722-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
The PIC18F6627/6722/8627/8722 parts you have
received conform functionally to the Device Data Sheet
(DS39646B), except for the anomalies described
below. Any Data Sheet Clarification issues related to
the PIC18F6627/6722/8627/8722 devices will be
reported in a separate Data Sheet errata. Please check
the Microchip web site for any existing issues.
All of the issues listed here will be addressed in future
revisions of the PIC18F6627/6722/8627/8722 silicon.
The
PIC18F6627/6722/8627/8722 devices with these
Device/Revision IDs:
1. Module: EUSART
© 2006 Microchip Technology Inc.
The Device IDs (DEVID1 and DEVID2) are located at
addresses
configuration space. They are shown in hexadecimal
in the format “DEVID2 DEVID1”.
Part Number
PIC18F6627
PIC18F6722
PIC18F8627
PIC18F8722
When performing back-to-back transmission in
9-bit mode (TX9D bit in the TXSTAx register is
set), an ongoing transmission’s timing can be
corrupted if the TX9D bit (for the next transmis-
sion) is not written immediately following the
setting of TXxIF. This is because any write to the
TXSTAx register results in a reset of the Baud
Rate Generator which will effect any ongoing
transmission.
Work around
Load TX9D just after TXxIF is set, either by polling
TXxIF or by writing TX9D at the beginning of the
Interrupt Service Routine, or only write to TX9D
when
(TRMT = 1).
Date Codes that pertain to this issue:
All engineering and production devices.
following
PIC18F6627/6722/8627/8722 Rev. A1 Silicon Errata
a
3FFFFEh:3FFFFFh
transmission
silicon
01 0100 000
01 0100 001
01 0011 110
01 0011 111
Device ID
errata apply
is
not
in
Revision ID
the
in
00000
00000
00000
00000
PIC18F6627/6722/8627/8722
only
device’s
progress
to
2. Module: Timer1/Timer3
3. Module: Timer1/Timer3
When Timer1/Timer3 is operating in 16-bit mode
and the prescale setting is not 1:1, a write to the
TMR1H/TMR3H Buffer registers may lengthen the
duration of the period between the increments of
the timer for the period in which TMR1H/TMR3H
was written.
Work around
Do not write to TMR1H/TMR3H while Timer1/
Timer3 is running, or else write to TMR1L/TMR3L
immediately following a write to TMR1H/TMR3H.
Do not write to TMR1H/TMR3H and then wait for
another event before also updating TMR1L/
TMR3L.
Date Codes that pertain to this issue:
All engineering and production devices.
When Timer1 or Timer3 is the time base for CCPx,
and the associated CCPxCON register is config-
ured with 0x0B (Compare mode, trigger special
event), the assigned timer is not reset on a Special
Event Trigger.
Work around
Modify firmware to reset the Timer registers
(TMRxL and TMRxH) upon detection of the
compare match condition.
Date Codes that pertain to this issue:
All engineering and production devices.
DS80221C-page 1

Related parts for PIC18F8722-E/PT

PIC18F8722-E/PT Summary of contents

Page 1

... Device/Revision IDs: Part Number Device ID PIC18F6627 01 0011 110 PIC18F6722 01 0100 000 PIC18F8627 01 0011 111 PIC18F8722 01 0100 001 The Device IDs (DEVID1 and DEVID2) are located at addresses 3FFFFEh:3FFFFFh in configuration space. They are shown in hexadecimal in the format “DEVID2 DEVID1”. 1. Module: EUSART When performing back-to-back transmission in 9-bit mode (TX9D bit in the TXSTAx register is set), an ongoing transmission’ ...

Page 2

... Work around Disable the PWM or set duty cycle to zero prior to switching directions. Date Codes that pertain to this issue: All engineering and production devices. Units Conditions LSb and V - REF REF REF LSb and V REF SS DD © 2006 Microchip Technology Inc. ...

Page 3

... WREG, BSR, STATUS for a second time Foo: POP ; clears return address of Foo call : ; insert high priority ISR code here : RETFIE FAST © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 Alternatively, in the case of MOVFF, use the MOVF instruction to write to WREG instead. For example, use: MOVF TEMP, W MOVWF BSR instead of MOVFF TEMP, BSR ...

Page 4

... EXAMPLE 3: OPTIMIZED INTERRUPT SERVICE ROUTINE #pragma code high_vector_section=0x8 void high_vector (void) { _asm CALL high_vector_branch, 1 _endasm } void high_vector_branch (void) { _asm POP GOTO high_isr _endasm } #pragma interrupt high_isr void high_isr (void) { ... } DS80221C-page 4 © 2006 Microchip Technology Inc. ...

Page 5

... EUSART transmits a shorter than expected clock on the CKx pin for the last bit transmitted. Work around None. © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 12. Module: EUSART In Synchronous mode, EUSART baud rates using SPBRGx values of ‘0’ and ‘1’ may not function correctly ...

Page 6

... SPI Slave mode, ensure that the SSPOV bit is clear before disabling the module. 20. Module: MSSP Master mode, the BRG value of ‘0’ may not work correctly. Work around Use a BRG value greater than ‘0’ by setting SSPxADD ≥ ‘1’. © 2006 Microchip Technology Inc. ...

Page 7

... Timer2 MOVWF SSPBUF ;Xmit New data BSF T2CON, TMR2ON ;Timer2 on © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 22. Module: Timer1 In 16-bit Asynchronous Counter mode or 16-bit Asynchronous Oscillator mode, the TMR1H and TMR3H buffers do not update when TMRxL is read. This issue only affects reading the TMRxH registers ...

Page 8

... Yes, reload for a 1 second overflow ;restore BSR register, refer to note 1 ;restore working register, refer to note 1 ;restore STATUS register (if Timer1 overflow occurred within CY T (μs) CY 15.25 μs 4 3.81 2 7.63 1 15.25 0.5 30.5 0.25 61 0.2 76.25 0.1 152.5 © 2006 Microchip Technology Inc. ...

Page 9

... TXREGx. Do not load the TXREGx when timer is about to overflow. Date Codes that pertain to this issue: All engineering and production devices. © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 27. Module: EUSART With the auto-wake-up option enabled by setting the WUE (BAUDCONx<1>) bit, the RCxIF bit will become set on a high-to-low transition on the RXx pin ...

Page 10

... C in Master /F ) – (F /1.111 MHz)) – SCL CY F SCL (2 Rollovers of BRG) (1) 400 kHz 15h 312.5 kHz 59h 100 kHz (1) 05h 400 kHz 08h 308 kHz 23h 100 kHz (1) 01h 333 kHz 08h 100 kHz (1) 00h 1 MHz © 2006 Microchip Technology Inc. ...

Page 11

... Date Codes that pertain to this issue: All engineering and production devices. © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 34. Module: ECCP (PWM Mode) When the PWM auto-shutdown feature is configured for automatic restart by setting the PxRSEN bit (ECCPxDEL< ...

Page 12

... Work around Two work arounds are available: 1. Use a latch based on the falling edge of ALE to hold the A<19:16> signals. 2. Add a delay circuit to extend the valid time for A<19:16> signals to ensure the address is valid until read/write signals go inactive. © 2006 Microchip Technology Inc. ...

Page 13

... Updated issue 7 (Interrupts) to include new code examples. Added silicon issues 25-27 (EUSART), 28-30 (MSSP – SPI Mode), 31-33 (MSSP – I (ECCP – PWM Mode), 36 (CCP – PWM Mode), 37 (Reset) and 38 (External Memory Bus). © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 2 C Mode), 34-35 DS80221C-page 13 ...

Page 14

... PIC18F6627/6722/8627/8722 NOTES: DS80221C-page 14 © 2006 Microchip Technology Inc. ...

Page 15

... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

Page 16

... Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2006 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-3910 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 ...

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