ATSAM3S2AA-AU Atmel, ATSAM3S2AA-AU Datasheet - Page 454
ATSAM3S2AA-AU
Manufacturer Part Number
ATSAM3S2AA-AU
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S2AA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
34
Ram Memory Size
32KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S2AA-AU
Manufacturer:
AMD
Quantity:
101
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26.16.10 PMC Clock Generator PLLB Register
Name:
Address:
Access:
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
This register can only be written if the WPEN bit is cleared in
• DIVB: Divider
• PLLBCOUNT: PLLB Counter
Specifies the number of Slow Clock cycles x8 before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• MULB: PLLB Multiplier
0 = The PLLB is deactivated.
1 up to 2047 = The PLLB Clock frequency is the PLLB input frequency multiplied by MULB + 1.
454
DIVB
0
1
2 - 255
31
23
15
–
–
7
SAM3S Preliminary
CKGR_PLLBR
0x400E042C
Read-write
30
22
14
–
–
6
29
21
13
–
5
Divider Selected
Divider output is 0
Divider is bypassed (DIVB=1)
Divider output is DIVB
28
20
12
–
4
MULB
DIVB
“PMC Write Protect Mode Register” on page
27
19
11
–
3
PLLBCOUNT
26
18
10
2
MULB
25
17
9
1
6500C–ATARM–8-Feb-11
466.
24
16
8
0
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