ATSAM3S2AA-AU Atmel, ATSAM3S2AA-AU Datasheet - Page 89
ATSAM3S2AA-AU
Manufacturer Part Number
ATSAM3S2AA-AU
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S2AA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 8x10/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
34
Ram Memory Size
32KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S2AA-AU
Manufacturer:
AMD
Quantity:
101
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10.12.2
10.12.2.1
10.12.2.2
10.12.2.3
10.12.2.4
6500C–ATARM–8-Feb-11
LDR and STR, immediate offset
Syntax
Operation
Offset addressing
Pre-indexed addressing
Load and Store with immediate offset, pre-indexed immediate offset, or post-indexed immediate
offset.
where:
op
type
cond
Rt
Rn
offset
Rt2
LDR instructions load one or two registers with a value from memory.
STR instructions store one or two register values to memory.
Load and store instructions with immediate offset can use the following addressing modes:
The offset value is added to or subtracted from the address obtained from the register Rn. The
result is used as the address for the memory access. The register Rn is unaltered. The assem-
bly language syntax for this mode is:
The offset value is added to or subtracted from the address obtained from the register Rn. The
result is used as the address for the memory access and written back into the register Rn. The
assembly language syntax for this mode is:
op{type}{cond} Rt, [Rn {, #offset}]
op{type}{cond} Rt, [Rn, #offset]!
op{type}{cond} Rt, [Rn], #offset
opD{cond} Rt, Rt2, [Rn {, #offset}]
opD{cond} Rt, Rt2, [Rn, #offset]!
opD{cond} Rt, Rt2, [Rn], #offset
[Rn, #offset]
LDR
STR
B
SB
H
SH
-
is one of:
Load Register.
Store Register.
is one of:
unsigned byte, zero extend to 32 bits on loads.
signed byte, sign extend to 32 bits (LDR only).
unsigned halfword, zero extend to 32 bits on loads.
signed halfword, sign extend to 32 bits (LDR only).
omit, for word.
is an optional condition code, see
is the register to load or store.
is the register on which the memory address is based.
is an offset from Rn. If offset is omitted, the address is the contents of Rn.
is the additional register to load or store for two-word operations.
“Conditional execution” on page
; immediate offset
; pre-indexed
; post-indexed
; immediate offset, two words
; pre-indexed, two words
; post-indexed, two words
SAM3S Preliminary
84.
89
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