AT89C5132-RORUL Atmel, AT89C5132-RORUL Datasheet - Page 123
AT89C5132-RORUL
Manufacturer Part Number
AT89C5132-RORUL
Description
MCU 8051 FLASH USB 80TQFP
Manufacturer
Atmel
Series
AT89C513xr
Specifications of AT89C5132-RORUL
Core Processor
C52X2
Core Size
8-Bit
Speed
20MHz
Connectivity
IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
Peripherals
I²S, POR, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Manufacturer
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Figure 19-5. Data Transmission Format (CPHA = 0)
Figure 19-6. Data Transmission Format (CPHA = 1)
19.1.5
4173E–USB–09/07
SS Management
MOSI (from Master)
MOSI (from Master)
SCK Cycle Number
SCK Cycle Number
MISO (from Slave)
MISO (from Slave)
to Capture Point
SCK (CPOL = 0)
SCK (CPOL = 1)
SCK (CPOL = 0)
SCK (CPOL = 1)
SPEN (Internal)
SPEN (Internal)
Capture Point
SS (to Slave)
SS (to Slave)
AT89C5132 captures data from the SI line while the selected slave captures data from the SO
line.
For simplicity, the following figures depict the SPI waveforms in idealized form and do not pro-
vide precise timing information. For timing parameters refer to the Section “AC Characteristics”.
Note:
Figure 19-5 shows an SPI transmission with CPHA = 0, where the first SCK edge is the MSB
capture point. Therefore the slave starts to output its MSB as soon as it is selected: SS asserted
to low level. SS must then be deasserted between each byte transmission (see Figure 19-7).
SPDAT must be loaded with data before SS is asserted again.
1. When the peripheral is disabled (SPEN = 0), default SCK line is high level.
MSB
MSB
MSB
MSB
1
1
bit 6
bit 6
bit 6
bit 6
2
2
bit 5
bit 5
bit 5
bit 5
3
3
bit 4
bit 4
bit 4
bit 4
4
4
bit 3
bit 3
bit 3
bit 3
5
5
bit 2
bit 2
bit 2
bit 2
6
6
bit 1
bit 1
bit 1
bit 1
7
7
LSB
LSB
LSB
8
8
LSB
AT89C5132
123
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