PIC18LF4680-I/PT Microchip Technology, PIC18LF4680-I/PT Datasheet - Page 2
![IC MCU FLASH 32KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18LF4680-I/PT
Manufacturer Part Number
PIC18LF4680-I/PT
Description
IC MCU FLASH 32KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4585-IPT.pdf
(482 pages)
4.PIC18F4585-IPT.pdf
(14 pages)
5.PIC18F4585-IPT.pdf
(8 pages)
6.PIC18F4585-IPT.pdf
(12 pages)
7.PIC18F4585-IPT.pdf
(4 pages)
Specifications of PIC18LF4680-I/PT
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
1024Byte
Ram Memory Size
3328Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4680-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F2585/2680/4585/4680
5. Module: ECCP
6. Module: ECCP
7. Module: ECCP
DS80202G-page 2
The auto-shutdown source, FLT0, has inverse
polarity from the description in Section 16.4.7
“Enhanced PWM Auto-Shutdown” of the Device
Data Sheet. A logic, high-voltage level on FLT0 will
generate a shutdown on ECCP1.
Work around
Invert the logic in the program’s source code.
Date Codes that pertain to this issue:
All engineering and production devices.
If a Halt command is issued while debugging with
the In-Circuit Debugger (MPLAB
ECCP module may freeze completely. However, if
a shutdown is enabled and triggered by the FLT0
pin, the ECCPASE bit is set and the outputs are
driven to their shutdown state, as defined by the
PSSAC1:PSSAC0 and PSSBD1:PSSBD0 bits,
regardless of the debugging process being
stopped.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
In 10-Bit Addressing mode, when a Repeated Start
is issued followed by the high address byte and a
Write command, an ACK is not issued.
Work around
There are two work arounds available:
1. Single-Master Environment:
2. Multi-Master Environment:
Date Codes that pertain to this issue:
All engineering and production devices.
In a single-master environment, the user must
issue a Stop, then a Start, followed by a write
to the address high, then the address low
followed by the data.
In a multi-master environment, the user must
issue a Repeated Start, send a dummy Write
command to a different address, issue another
Repeated Start and then send a write to the
original address. This procedure will prevent
loss of the bus.
®
ICD 2), the
8. Module: ECCP and CCP
9. Module: Timer1/Timer3
10. Module: Timer1/Timer3
When ECCP1 and CCP1 are configured for PWM
mode, with 1:1 Timer2 prescaler and duty cycle set
to the period minus 1, this may result in the PWM
output(s) remaining at a logic low level.
Clearing the PR2 register to select the fastest
period may also result in the output(s) remaining at
a logic low output level.
Work around
To ensure a reliable waveform, verify that the
selected duty cycle does not equal the 10-bit
period minus 1 prior to writing these locations, or
use 1:4 or 1:16 Timer2 prescale. Also, verify the
PR2 register is not written to 00h.
All other duty cycle and period settings will function
as described in the Device Data Sheet.
The ECCP and CCP modules remain capable of
10-bit accuracy.
Date Codes that pertain to this issue:
All engineering and production devices.
When Timer1 or Timer3 is configured for an
external clock source and the CCP1CON or
ECCP1CON register is configured with 0x0B
(Compare mode, trigger special event), the timer is
not reset on a Special Event Trigger.
Work around
Modify firmware to reset the Timer registers upon
detection of the compare match condition – TMRxL
and TMRxH.
Date Codes that pertain to this issue:
All engineering and production devices.
When the Timer1/Timer3 is in External Clock
Synchronized mode and the external clock period
is between 1 and 2 T
occasionally be skipped.
Work around
None
Date Codes that pertain to this issue:
All engineering and production devices.
© 2007 Microchip Technology Inc.
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