PIC18F8622-I/PT Microchip Technology, PIC18F8622-I/PT Datasheet - Page 443

• Manufacturer Part Number: PIC18F8622-I/PT
• Description: IC PIC MCU FLASH 32KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8622-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 80-TFQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 70
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI/I2C/EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 70
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timing Diagrams and Specifications
 2004 Microchip Technology Inc.
Parallel Slave Port
Parallel Slave Port (PSP) Read ............................... 160
Parallel Slave Port (PSP) Write ............................... 160
Program Memory Read ............................................ 403
Program Memory Write ............................................ 404
PWM Auto-Shutdown (P1RSEN = 0,
PWM Auto-Shutdown (P1RSEN = 1,
PWM Direction Change ........................................... 199
PWM Direction Change at
PWM Output ............................................................ 184
Repeated Start Condition ......................................... 235
Reset, Watchdog Timer (WDT),
Send Break Character Sequence ............................ 263
Slave Synchronization ............................................. 211
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 210
SPI Mode (Slave Mode, CKE = 0) ........................... 212
SPI Mode (Slave Mode, CKE = 1) ........................... 212
Synchronous Reception
Synchronous Transmission ...................................... 264
Synchronous Transmission
Time-out Sequence on POR w/PLL
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up (MCLR
Timer0 and Timer1 External Clock .......................... 406
Transition for Entry to Idle Mode ................................ 46
Transition for Entry to SEC_RUN Mode .................... 43
Transition for Entry to Sleep Mode ............................ 45
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 46
Transition for Wake from Sleep (HSPLL) ................... 45
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 44
Typical Opcode Fetch, 8-bit Mode ........................... 108
A/D Conversion Requirements ................................ 419
AC Characteristics
Capture/Compare/PWM Requirements
(PIC18F8527/8622/8627/8722) ....................... 408
Auto-Restart Disabled) .................................... 202
Auto-Restart Enabled) ..................................... 202
Near 100% Duty Cycle .................................... 199
Oscillator Start-up Timer (OST) and
Power-up Timer (PWRT) ................................. 405
V
(Master Mode, SREN) ..................................... 266
(Through TXEN) .............................................. 265
Enabled (MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
Tied to V
(INTOSC to HSPLL) ........................................ 314
PRI_RUN Mode ................................................. 44
PRI_RUN Mode (HSPLL) .................................. 43
Internal RC Accuracy ....................................... 401
(All ECCP/CCP Modules) ................................ 407
DD
Rise > T
DD
, V
PWRT
DD
Rise < T
) ............................................ 55
DD
DD
, Case 1) ....................... 54
, Case 2) ....................... 54
DD
PWRT
DD
) ............................. 55
,
) ........................ 54
Preliminary
Top-of-Stack Access .......................................................... 66
TRISE Register
TSTFSZ ........................................................................... 361
Two-Speed Start-up ................................................. 297, 314
Two-Word Instructions
TXSTAx Register
W
Watchdog Timer (WDT) ........................................... 297, 312
WCOL ...................................................... 234, 235, 236, 239
WCOL Status Flag ................................... 234, 235, 236, 239
WWW, On-Line Support ...................................................... 5
X
XORLW ........................................................................... 361
XORWF ........................................................................... 362
PIC18F8722 FAMILY
CLKO and I/O Requirements ........................... 402, 403
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode
External Clock Requirements .................................. 400
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements
PLL Clock ................................................................ 401
Program Memory Write Requirements .................... 404
Reset, Watchdog Timer,
Timer0 and Timer1 External
PSPMODE Bit ......................................................... 158
IESO (CONFIG1H<7>), Internal/External
Example Cases ......................................................... 71
BRGH Bit ................................................................. 251
Associated Registers ............................................... 313
Control Register ....................................................... 312
During Oscillator Failure .......................................... 315
Programming Considerations .................................. 312
2
2
C Bus Data Requirements (Slave Mode) .............. 414
C Bus Start/Stop Bits Requirements
Requirements .................................................. 417
Requirements .................................................. 417
(Master Mode, CKE = 0) .................................. 409
(Master Mode, CKE = 1) .................................. 410
(Slave Mode, CKE = 0) .................................... 411
Requirements (CKE = 1) ................................. 412
(Slave Mode) ................................................... 413
Requirements .................................................. 415
(PIC18F8527/8622/8627/8722) ....................... 408
Oscillator Start-up Timer,
Power-up Timer and
Brown-out Reset Requirements ...................... 405
Clock Requirements ........................................ 406
Oscillator Switchover Bit................................... 299
2
2
C Bus Data Requirements ................ 416
C Bus Start/Stop Bits
DS39646B-page 441