DSPIC30F6012A-20E/PF Microchip Technology, DSPIC30F6012A-20E/PF Datasheet - Page 37

• Manufacturer Part Number: DSPIC30F6012A-20E/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-20E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 144KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 68
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. Should
a misaligned read or write be attempted, an address
error trap will be generated. If the error occurred on a
read, the instruction underway is completed, whereas if
it occurred on a write, the instruction will be executed
but the write will not occur. In either case, a trap will
then be executed, allowing the system and/or user to
examine the machine state prior to execution of the
address fault.
FIGURE 3-10:
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A sign-extend (SE) instruction is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, users
can clear the MSB of any W register by executing a
zero-extend (ZE) instruction on the appropriate
address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions, including the DSP instructions, operate
only on words.
3.2.5
An 8 Kbyte ‘near’ data space is reserved in X address
memory space between 0x0000 and 0x1FFF, which is
directly addressable via a 13-bit absolute address field
within all memory direct instructions. The remaining X
address space and all of the Y address space is
addressable indirectly. Additionally, the whole of X data
space is addressable using MOV instructions, which
support memory direct addressing with a 16-bit
address field.
© 2008 Microchip Technology Inc.
0001
0003
0005
15
NEAR DATA SPACE
Byte1
Byte3
Byte5
MSB
DATA ALIGNMENT
dsPIC30F6011A/6012A/6013A/6014A
8 7
Byte 0
Byte 2
Byte 4
LSB
0
0000
0002
0004
3.2.6
The dsPIC DSC devices contain a software stack. W15
is used as the Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops and
post-increments for stack pushes as shown in
Figure 3-11. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear.
There is a Stack Pointer Limit register (SPLIM)
associated
uninitialized at Reset. As is the case for the Stack
Pointer, SPLIM<0> is forced to ‘0’ because all stack
operations must be word aligned. Whenever an
Effective Address (EA) is generated using W15 as a
source or destination pointer, the address thus
generated is compared with the value in SPLIM. If the
contents of the Stack Pointer (W15) and the SPLIM reg-
ister are equal and a push operation is performed, a
Stack Error Trap will not occur. The Stack Error Trap will
occur on a subsequent push operation. Thus, for exam-
ple, if it is desirable to cause a Stack Error Trap when
the stack grows beyond address 0x2000 in RAM,
initialize the SPLIM with the value, 0x1FFE.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800, thus preventing the stack from
interfering with the Special Function Register (SFR)
space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 3-11:
0x0000
Note:
15
000000000
SOFTWARE STACK
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
with
<Free Word>
PC<15:0>
the
PC<22:16>
CALL STACK FRAME
Stack
0
Pointer.
POP : [--W15]
PUSH : [W15++]
W15 (before CALL)
W15 (after CALL)
DS70143D-page 37
SPLIM
is