PIC16F877-20I/L Microchip Technology, PIC16F877-20I/L Datasheet - Page 665
![IC MCU FLASH 8KX14 EE 44PLCC](/photos/6/63/66325/150-44-plcc_sml.jpg)
PIC16F877-20I/L
Manufacturer Part Number
PIC16F877-20I/L
Description
IC MCU FLASH 8KX14 EE 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16C770-ISO.pdf
(8 pages)
4.PIC16F873-04SO.pdf
(218 pages)
5.PIC16F873-04SO.pdf
(5 pages)
6.PIC16F873-04SO.pdf
(5 pages)
Specifications of PIC16F877-20I/L
Core Size
8-Bit
Program Memory Size
14KB (8K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Controller Family/series
PIC16F
No. Of I/o's
33
Eeprom Memory Size
256Byte
Ram Memory Size
368Byte
Cpu Speed
20MHz
No. Of Timers
3
Embedded Interface Type
I2C, PSP, SPI, USART
A/d Converter
10 Bits
No. Of Timers 8/12/16/32 Bits
2 / 0 / 1 / 0
Interface
I2C, PSP, SPI, USART
Rohs Compliant
No
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
368 B
Interface Type
MSSP, PSP, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
33
Number Of Timers
3
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163022, DV164120
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164309 - MODULE SKT FOR PM3 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCC309-1040 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1039 - ADAPTER 44-PLCC TO 40-DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / Rohs Status
Details
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- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- PIC16F873-04SO PDF datasheet #6
- Current page: 665 of 688
- Download datasheet (3Mb)
APPENDIX C: DEVICE ENHANCEMENT
C.1
1997 Microchip Technology Inc.
Data Memory Map
As the Midrange architecture matured, certain modules and features have been enhanced. They
are:
1.
2.
3.
4.
5.
6.
7.
The following subsections discuss the implementations of these enhancements.
The Data Memory Map shows the location of the Special Function Registers (SFRs) and the
General Purpose Registers (GPRs). SFRs provide controls and give status on the operation of
the device, while the GPRs are the general purpose RAM.
Figure C-1
Memory Map A was implemented on the first midrange devices. They were 18/20-pin devices
that had limited peripheral features. When the product roadmap dictated the requirement for
devices with increased I/O, and a richer peripheral set, memory map B was implemented. Mem-
ory map C is actually a subset of memory map B, but context saving (due to an interrupt) requires
additional software overhead. This is because there is no GPR in Bank1. To minimize the context
saving software, memory map D was defined. A common RAM memory map will be used for all
future devices. See the
Midrange PICmicro’s memory.
Figure C-1:
A
The data memory map
The SSP module
The A/D module
Brown-out Reset added to the core
MCLR Filter
USART
Device Oscillator
0Ch
Note 1: Mapped in Bank0.
0Bh
00h
7Fh
1Fh
7Fh
00h
20h
70h
Bank0 Bank1
GPR
2: Unimplemented, read as '0'.
3: Some devices have some GPR located in the SFR region.
SFR
show the various memory maps that have been implemented in the midrange family.
D
Bank0
SFR
GPR
(3)
SFR
Various Data Memory Maps
(1)
80h
9Fh
A0h
F0h
FFh
80h
8Bh
8Ch
FFh
“Memory Organization”
Bank1
GPR
SFR
(1)
1Fh
7Fh
00h
20h
170h
17Fh
100h
11Fh
120h
B
Bank0 Bank1
GPR
SFR
Bank2
GPR
SFR
(1)
GPR
SFR
180h
19Fh
1A0h
1F0h
1FFh
section for use and implementation of the
80h
9Fh
A0h
FFh
Bank3
GPR
SFR
(1)
1Fh
7Fh
Appendix C
00h
20h
Bank0 Bank1
C
GPR
SFR
DS31034A-page 34-13
SFR
(2)
80h
9Fh
A0h
FFh
34
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