PIC18F6627-I/PT Microchip Technology, PIC18F6627-I/PT Datasheet
PIC18F6627-I/PT
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PIC18F6627-I/PT Summary of contents
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... PIC18F6627/6722/8627/8722 Rev. A1 Silicon Errata The PIC18F6627/6722/8627/8722 parts you have received conform functionally to the Device Data Sheet (DS39646B), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F6627/6722/8627/8722 devices will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues ...
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... PIC18F6627/6722/8627/8722 4. Module: A/D The A/D offset is greater than the specified limit in Table 28-26 of the Device Data Sheet. The updated conditions and limits are shown in bold text in Table 1. Work around Three work arounds exist: 1. Configure the A/D to use the V pins for the voltage references. This is done by setting the VCFG< ...
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... POP ; clears return address of Foo call : ; insert high priority ISR code here : RETFIE FAST © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 Alternatively, in the case of MOVFF, use the MOVF instruction to write to WREG instead. For example, use: MOVF TEMP, W MOVWF BSR instead of MOVFF TEMP, BSR. ...
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... PIC18F6627/6722/8627/8722 EXAMPLE 2: INTERRUPT SERVICE ROUTINE IN C #pragma interruptlow MyLowISR void MyLowISR(void Handle low priority interrupts Although MyHighISR is a high priority interrupt, use interruptlow pragma so that // the compiler will not use retfie FAST. #pragma interruptlow MyHighISR void MyHighISR(void Handle high priority interrupts. ...
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... CKx pin for the last bit transmitted. Work around None. © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 12. Module: EUSART In Synchronous mode, EUSART baud rates using SPBRGx values of ‘0’ and ‘1’ may not function correctly. Work around Use another baud rate configuration to generate the desired baud rate ...
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... PIC18F6627/6722/8627/8722 16. Module: External Memory Bus For PIC18F8XXX devices, the Stack Pointer may incorrectly increment during a table read operation if external memory bus wait states are enabled (i.e., Configuration bit, WAIT, is clear (CONFIG3L<7> and WAIT<1:0> bits (MEMCON<5:4>) are not equal to ‘11’). Work around ...
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... MOVWF SSPBUF ;Xmit New data BSF T2CON, TMR2ON ;Timer2 on © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 22. Module: Timer1 In 16-bit Asynchronous Counter mode or 16-bit Asynchronous Oscillator mode, the TMR1H and TMR3H buffers do not update when TMRxL is read. This issue only affects reading the TMRxH registers ...
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... PIC18F6627/6722/8627/8722 24. Module: Timer1 (Asynchronous Counter) When writing to the TMR1H register, under specific conditions possible that the TMR1L register will miss a count while connected to the external oscillator via the T1OSO and T1OSI pins. When Timer1 is started, the circuitry looks for a falling edge before a rising edge can increment the counter. Writing to the TMR1H register is similar to starting Timer1 ...
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... TXREGx when timer is about to overflow. Date Codes that pertain to this issue: All engineering and production devices. © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 27. Module: EUSART With the auto-wake-up option enabled by setting the WUE (BAUDCONx<1>) bit, the RCxIF bit will become set on a high-to-low transition on the RXx pin ...
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... PIC18F6627/6722/8627/8722 29. Module: MSSP (SPI Mode) In SPI mode, the Buffer Full Status bit, BF (SSPxSTAT<0>), should not be polled in software to determine when the transfer is complete. Work around Copy the SSPxSTAT register into a variable and perform the bit test on the variable. In Example 7, SSPxSTAT is copied into the working register ...
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... Date Codes that pertain to this issue: All engineering and production devices. © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 34. Module: ECCP (PWM Mode) When the PWM auto-shutdown feature is configured for automatic restart by setting the PxRSEN bit (ECCPxDEL<7>), the pulse may terminate immediately in a shutdown event ...
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... PIC18F6627/6722/8627/8722 37. Module: Reset This version of silicon does not support the func- tionality described in Note 1 of parameter D002 in Section 28.1 “DC Characteristics: Supply Voltage” of the data sheet. The RAM content may be altered during a Reset event if the following conditions are met. • Device is accessing RAM. ...
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... Updated issue 7 (Interrupts) to include new code examples. Added silicon issues 25-27 (EUSART), 28-30 (MSSP – SPI Mode), 31-33 (MSSP – I (ECCP – PWM Mode), 36 (CCP – PWM Mode), 37 (Reset) and 38 (External Memory Bus). © 2006 Microchip Technology Inc. PIC18F6627/6722/8627/8722 2 C Mode), 34-35 DS80221C-page 13 ...
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... PIC18F6627/6722/8627/8722 NOTES: DS80221C-page 14 © 2006 Microchip Technology Inc. ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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