AT89C51CC03UA-RDTUM Atmel, AT89C51CC03UA-RDTUM Datasheet - Page 28
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AT89C51CC03UA-RDTUM
Manufacturer Part Number
AT89C51CC03UA-RDTUM
Description
IC 8051 MCU FLASH 64K 64-VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheet
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
Specifications of AT89C51CC03UA-RDTUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
2
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64VQFP
Device Core
8051
Family Name
AT89
Maximum Speed
60 MHz
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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AT89C51CC03
Reset Value = X001 0100b
Not bit addressable
Table 8. AUXR1 Register
AUXR1 (S:A2h)
Auxiliary Control Register 1
Reset Value = XXXX 00X0b
Number
Number
Bit
Bit
4-2
7-6
7
-
1
0
5
4
3
2
1
0
Mnemonic Description
Mnemonic Description
EXTRAM
ENBOOT
XRS1-0
DPS
GF3
Bit
Bit
A0
6
-
0
-
-
-
ERAM size:
Accessible size of the ERAM
XRS 2:0 ERAM size
000
001
010
011
100
101
110
111
Internal/External RAM (00h - FFh)
access using MOVX @ Ri/@ DPTR
0 - Internal ERAM access using MOVX @ Ri/@ DPTR.
1 - External data memory access.
Disable/Enable ALE)
0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2
mode is used)
1 - ALE is active only during a MOVX or MOVC instruction.
Reserved
The value read from these bits is indeterminate. Do not set these bits.
Enable Boot Flash
Set this bit for map the boot Flash between F800h -FFFFh
Clear this bit for disable boot Flash.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
General-purpose Flag 3
Always Zero
This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3
flag.
Reserved for Data Pointer Extension.
Data Pointer Select Bit
Set to select second dual data pointer: DPTR1.
Clear to select first dual data pointer: DPTR0.
ENBOOT
5
256 Bytes
512 Bytes
768 Bytes
1792 Bytes
2048 Bytes (default configuration after reset)
Reserved
1024 Bytes
Reserved
4
-
GF3
3
2
0
4182O–CAN–09/08
1
-
DPS
0
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