AT89C51CC03UA-RDTUM Atmel, AT89C51CC03UA-RDTUM Datasheet - Page 52
AT89C51CC03UA-RDTUM
Manufacturer Part Number
AT89C51CC03UA-RDTUM
Description
IC 8051 MCU FLASH 64K 64-VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheet
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
Specifications of AT89C51CC03UA-RDTUM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
2
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
64VQFP
Device Core
8051
Family Name
AT89
Maximum Speed
60 MHz
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Reset the Column Latches
Error Reports
Flash Programming Sequence
Errors
52
AT89C51CC03
Figure 27. Hardware Programming Procedure
An automatic reset of the column latches is performed after a successful Flash
write sequence. User can also reset the column latches manually, for instance
to reload the column latches before writing the Flash. The following procedure is
summarized below.
•
•
•
When a wrong sequence is detected, the SEQERR bit in FSTA register is set. Possible
wrong sequence are :
•
•
The SEQERR bit can be cleared
•
•
When multiple pages are written into the Flash, the user should check FSTA for errors
after each write page sequences, not only at the end of the multiple write pages.
Save and disable the interrupts.
Launch the reset by writing the data sequence 56h followed by A6h in FCON
register (only from FM1).
Restore the interrupts.
MOV FCON, 5xh instruction not immediately followed by a MOV FCON, Ax
instruction.
A write Flash sequence is launched while no data were loaded in the column latches
By software
By hardware when a correct programming sequence is completed
Exec: MOVX @DPTR, A
Save and Disable IT
Programming
Flash Spaces
End Loading
FCON = 0Ch
DPTR = 00h
ACC = Data
Data Load
Restore IT
EA = 0
Launch Programming
Save and Disable IT
End Programming
FCON = A4h
FCON = 54h
FCON = 00h
Clear Mode
4182O–CAN–09/08
Cleared?
RestoreIT
FBusy
EA = 0
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