PIC18C858-E/PT Microchip Technology, PIC18C858-E/PT Datasheet - Page 9
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PIC18C858-E/PT
Manufacturer Part Number
PIC18C858-E/PT
Description
IC MCU OTP 16KX16 CAN 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16C770-ISO.pdf
(8 pages)
3.PIC18C658-IPT.pdf
(366 pages)
4.PIC18C658-IPT.pdf
(16 pages)
5.PIC18C658-IPT.pdf
(16 pages)
6.PIC18C658-IPT.pdf
(16 pages)
Specifications of PIC18C858-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
3-Wire, I2C, SPI, USART, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
68
Number Of Timers
4 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
ICE2000, DM163007, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
6
Data Rom Size
4 KB
Height
1 mm
Length
12 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.2 V
Width
12 mm
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C858E/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C858-E/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C858-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
5. Module: Interrupts
REGISTER 7-1:
FIGURE 1:
2003 Microchip Technology Inc.
The operation of the GIE/GIEH bit (INTCON<7>) is
clarified as follows: when the bit is cleared, all
interrupts are disabled. This is regardless of the
state of the IPEN bit (RCON<7>), the priority of the
interrupt, or whether or not the interrupt is
unmasked. This varies from the original descrip-
tion, in which clearing the bit when IPEN = 1 would
only disable high priority interrupts.
The seventh paragraph in Section 7.0 of the
Device Data Sheet (beginning “When an interrupt
is responded to....”) is amended by adding the fol-
lowing sentence to the end:
Low Priority Interrupt Generation
Peripheral Interrupt Enable bit
Peripheral Interrupt Priority bit
Peripheral Interrupt Flag bit
bit 7
TMR1IE
TMR1IP
TMR1IF
XXXXIE
XXXXIP
XXXXIF
INTERRUPT LOGIC (EXCERPT)
INTCON REGISTER (EXCERPT)
GIE/GIEH: Global Interrupt Enable bit
When IPEN (RCON<7>) = 0:
1 = Enables all unmasked interrupts
0 = Disables all interrupts
When IPEN (RCON<7>) = 1:
1 = Enables all high priority interrupts
0 = Disables all interrupts
Additional Peripheral Interrupts
TMR0IE
TMR0IP
TMR0IF
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RBIF
RBIE
RBIP
“It is important to note, however, that clearing the
GIE/GIEH bit, regardless of the state of the IPEN
bit, will disable all interrupts.”
The changes to the bit descriptions in Register 7-1
in the Device Data Sheet are shown in the excerpt
below (changes in bold).
Also, the interrupt logic funnel shown in Figure 7-1
of the Device Data Sheet is amended with the
addition of a GIE/GIEH control line, as shown in
Figure 1 (new material in bold line).
PIC18C658/858
GIEL/PEIE
GIE/GEIH
DS80126C-page 9
Interrupt to CPU
Vector to Location
0018h