PIC17C756A-33E/L Microchip Technology, PIC17C756A-33E/L Datasheet - Page 174
![IC MCU CMOS 33MHZ 16K EPRM68PLCC](/photos/12/13/121323/c04-049_l_sml.jpg)
PIC17C756A-33E/L
Manufacturer Part Number
PIC17C756A-33E/L
Description
IC MCU CMOS 33MHZ 16K EPRM68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(6 pages)
Specifications of PIC17C756A-33E/L
Core Processor
PIC
Core Size
8-Bit
Speed
33MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
68-PLCC
Processor Series
PIC17C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
902 B
Interface Type
I2C, MSSP, RS- 232, SCI, SPI, USART
Maximum Clock Frequency
33 MHz
Number Of Programmable I/os
50
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC17C756A-33E/L
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC17C756A-33E/L
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC17C7XX
15.2.18.3
Bus collision occurs during a STOP condition if:
a)
b)
FIGURE 15-40:
FIGURE 15-41:
DS30289B-page 174
After the SDA pin has been de-asserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is de-asserted, SCL is sam-
pled low before SDA goes high.
SDA
SCL
PEN
BCLIF
P
SSPIF
SSPIF
BCLIF
SDA
PEN
SCL
Bus Collision During a STOP
Condition
P
’0’
’0’
’0’
’0’
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
Assert SDA.
T
SDA asserted low.
BRG
T
BRG
T
BRG
T
BRG
The STOP condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the baud rate generator is loaded with SSPADD<6:0>
and counts down to ‘0’. After the BRG times out, SDA
is sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data '0'. If the SCL pin is sampled low before
SDA is allowed to float high, a bus collision occurs. This
is another case of another master attempting to drive a
data '0' (Figure 15-40).
SCL goes low before SDA goes high.
Set BCLIF.
T
BRG
T
BRG
2000 Microchip Technology Inc.
’0’
’0’
SDA sampled
low after T
Set BCLIF.
BRG
,
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