ATXMEGA256A3B-MH Atmel, ATXMEGA256A3B-MH Datasheet - Page 98
![MCU AVR 256KB FLASH A3B 64-QFN](/photos/12/13/121326/313-64-qfn_sml.jpg)
ATXMEGA256A3B-MH
Manufacturer Part Number
ATXMEGA256A3B-MH
Description
MCU AVR 256KB FLASH A3B 64-QFN
Manufacturer
Atmel
Series
AVR® XMEGAr
Specifications of ATXMEGA256A3B-MH
Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
49
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
Processor Series
ATXMEGA256x
Core
AVR8
Data Bus Width
8 bit, 16 bit
Data Ram Size
16 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
49
Number Of Timers
7
Operating Supply Voltage
1.6 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 8 Channel
On-chip Dac
12 bit, 2 Channel
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
ATXMEGA256A3B-MU
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA256A3B-MH
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
8116I–AVR–09/10
12. DAC refresh may be blocked in S/H mode
13. Conversion lost on DAC channel B in event triggered mode
14. EEPROM page buffer always written when NVM DATA0 is written
15. Pending full asynchronous pin change interrupts will not wake the device
16. Pin configuration does not affect Analog Comparator output
17. NMI Flag for Crystal Oscillator Failure automatically cleared
If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is
done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this
will block refresh signals to the second channel.
Problem fix/Workaround
When using the DAC in S/H mode, ensure that none of the channels is running at maximum
conversion rate, or ensure that the conversion rate of both channels is high enough to not
require refresh.
If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1
conversions are occasionally lost. This means that not all data-values written to the
Channel 1 data register are converted.
Problem fix/Workaround
Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Periph-
eral clock frequency so the conversion internal never is shorter than 1.5 µs.
If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM
page buffer.
Problem fix/Workaround
Before writing to NVM DATA0, for example when doing software CRC or flash page buffer
write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM
DATA0 when EELOAD is set.
Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the
sleep instruction is executed, will be ignored until the device is woken from another source
or the source triggers again. This applies when entering all sleep modes where the System
Clock is stopped.
Problem fix/Workaround
None.
The Output/Pull and inverted pin configuration does not affect the Analog Comparator
output.
Problem fix/Workaround
None for Output/Pull configuration.
For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect
positive input to the negative AC input and vice versa), or use and external inverter to
change polarity of Analog Comparator output.
NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when exe-
cuting the NMI interrupt handler.
XMEGA A3B
98