ATSAM3U2EA-AU Atmel, ATSAM3U2EA-AU Datasheet - Page 190
![IC MCU 32BIT 128KB FLASH 144LQFP](/photos/6/72/67244/144l1-lqfp_sml.jpg)
ATSAM3U2EA-AU
Manufacturer Part Number
ATSAM3U2EA-AU
Description
IC MCU 32BIT 128KB FLASH 144LQFP
Manufacturer
Atmel
Series
SAM3Ur
Specifications of ATSAM3U2EA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
96MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b, 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Controller Family/series
SAM3U
No. Of I/o's
96
Ram Memory Size
36KB
Cpu Speed
96MHz
No. Of Timers
3
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
36 KB
Interface Type
4xUSART, 2xTWI, 5xSPI, Bus
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
96
Number Of Timers
8
Operating Supply Voltage
1.62 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3U-EK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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13.20.8
• STKALIGN
Indicates stack alignment on exception entry:
0 = 4-byte aligned
1 = 8-byte aligned.
On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the excep-
tion it uses this stacked bit to restore the correct stack alignment.
• BFHFNMIGN
Enables handlers with priority -1 or -2 to ignore data bus faults caused by load and store instructions. This applies to the
hard fault and FAULTMASK escalated handlers:
0 = data bus faults caused by load and store instructions cause a lock-up
1 = handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.
Set this bit to 1 only when the handler and its data are in absolutely safe memory. The normal use of this bit is to probe sys-
tem devices and bridges to detect control path problems and fix them.
• DIV_0_TRP
Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0:
0 = do not trap divide by 0
1 = trap divide by 0.
When this bit is set to 0,a divide by zero returns a quotient of 0.
• UNALIGN_TRP
Enables unaligned access traps:
0 = do not trap unaligned halfword and word accesses
190
31
23
15
7
SAM3U Series
Configuration and Control Register
Reserved
30
22
14
6
The CCR controls entry to Thread mode and enables:
See the register summary in
The bit assignments are:
• the handlers for hard fault and faults escalated by FAULTMASK to ignore bus faults
• trapping of divide by zero and unaligned accesses
• access to the STIR by unprivileged software, see
page
177.
29
21
13
5
Reserved
DIV_0_TRP
28
20
12
4
Table 13-30 on page 180
Reserved
Reserved
UNALIGN_T
RP
27
19
11
3
“Software Trigger Interrupt Register” on
Reserved
for the CCR attributes.
26
18
10
2
USERSETM
STKALIGN
PEND
25
17
9
1
6430D–ATARM–25-Mar-11
BFHFNMIGN
NONBASET
HRDENA
24
16
8
0
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