DSPIC30F6012T-20E/PF Microchip Technology, DSPIC30F6012T-20E/PF Datasheet - Page 4

• Manufacturer Part Number: DSPIC30F6012T-20E/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012T-20E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TQFP, 64-VQFP
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DSPIC30F6012T20EP

dsPIC30F6011/6012/6013/6014
TABLE 2:
DS80456D-page 4
Note 1:
Controller
Program
Interrupt
Memory
Module
PWM
PWM
ADC
CPU
ADC
QEI
Only those issues indicated in the last column apply to the current silicon revision.
Consumption
Index Pulse
Operations
IPC2 Write
Sequential
Time Base
Prescalers
Sequence
I
Sampling
Override
Feature
PD
in Sleep
SILICON ISSUE SUMMARY (CONTINUED)
Current
Current
Output
RTSP
Mode
Mode
Sleep
Number
Item
35.
36.
37.
38.
39.
40.
41.
42.
A specific write sequence for Interrupt Priority Control 2 (IPC2)
SFR is required.
RTSP operations may not be performed on the Program Memory.
RTSP operations can however be performed on the on-chip Data
EEPROM.
Sampling multiple channels sequentially using any conversion
trigger other than the auto-convert feature requires SAMC bits to
be non-zero.
The Reset on Index Pulse Mode does not work.
The Motor Control PWM Time base prescaler options: 1:4, 1:16
and 1:64 may produce unexpected results when used to
generate center-aligned PWM pulses.
The output override function of the PWM module, controlled by
the OVDCON register and the OSYNC bit (PWMCON2<1>),
produces unexpected results in certain cases when the module
is used in Complementary mode.
The device exhibits I
arounds are required to achieve I
If the ADC module is in an enabled state when the device enters
Sleep Mode, the power-down current (I
exceed the device data sheet specifications.
PD
Issue Summary
less than 0.1 μA. However, certain work
PD
in this range.
PD
) of the device may
© 2010 Microchip Technology Inc.
Revisions
A3 B1 B2
X
X
X
X
X
X
X
X
Affected
X
X
X
(1)