DSPIC30F6013T-20E/PF Microchip Technology, DSPIC30F6013T-20E/PF Datasheet - Page 22
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DSPIC30F6013T-20E/PF
Manufacturer Part Number
DSPIC30F6013T-20E/PF
Description
IC DSPIC MCU/DSP 132K 80TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F6014-20IPF.pdf
(228 pages)
2.DSPIC30F6014-20IPF.pdf
(22 pages)
3.DSPIC30F6014-20IPF.pdf
(28 pages)
Specifications of DSPIC30F6013T-20E/PF
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
132KB (44K x 24)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
For Use With
DM300024 - KIT DEMO DSPICDEM 1.1AC164314 - MODULE SKT FOR PM3 80PFAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F6013T20EP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6013T-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
dsPIC30F6011/6012/6013/6014
34. Module: CAN
35. Module: Interrupt Controller
EXAMPLE 18:
EXAMPLE 19:
DS80456D-page 22
mov
mov
disi #2
mov
mov
asm volatile(
//Note: There are no commas between
//
//
CAN Receive filters 3, 4 and 5 may not work for a
given combination of instruction cycle speed and
CAN bit time quanta.
Work around
Do not use CAN RX filters 3, 4 and 5. Instead, use
filters 0, 1 and 2.
Affected Silicon Revisions
A specific write sequence for Interrupt Priority
Control 2 (IPC2) SFR is required to prevent
possible data corruption in the Interrupt Enable
Control 2 (IEC2) SFR. Interrupts must be disabled
during this IPC2 SFR write sequence.
Work around
An example of this write sequence is shown in
Example 18.
When coding in C, the write sequence shown
above can be implemented using inline assembly
instructions. The equivalent write sequence using
the C30 compiler is shown in Example 19.
Affected Silicon Revisions
A3
A3
#IPC2, w0
#0x4444, w1
w1, IPC2
#IPC2, w0
X
X
the quoted strings in the code
segment above.
B1
B1
X
X
B2
B2
“mov.d w0, [w15++]\n\t”
“mov
“mov
“disi
“mov
“mov
“mov.d [--w15], w0”);
X
;Point w0 to IPC2
;Write data to go to IPC2
;Disable interrupts for
;next two cycles
;Write the data to IPC2
;Target w1 to keep IPC2
;address on bus
#IPC2,w0\n\t”
#0x4444,w1\n\t”
#2\n\t”
w1, IPC2\n\t”
#IPC2, w0\n\t”
36. Module: Program Memory
37. Module: ADC
For this revision of silicon, run-time self-
programming operations should not be performed
on the User Program Memory and Configuration
Fuse bits. Configuration Fuse bits may be pro-
grammed within the MPLAB IDE using a device
programmer, for example, MPLAB ICD 2.
Note that the on-chip Data EEPROM can be
self-programmed at run-time.
Work around
None.
Affected Silicon Revisions
Sampling multiple channels sequentially using any
conversion trigger source other than the auto-convert
feature requires SAMC bits to be non-zero. Thus, if
the following conditions are all satisfied, the module
may not operate as specified:
- Multiple S/H channels are sampled
- Auto-convert option is not chosen as the
- SAMC (ADCON3<12:8>) is equal to ‘00000’
Work around
Set the value of the SAMC bits to anything other
than ‘00000’. The module will now operate as
specified.
Affected Silicon Revisions
A3
A3
X
X
sequentially
CHPS (ADCON2<9:8>) is not equal to ‘00’ and
SIMSAM (ADCON1<3>) = 0
conversion trigger
SSRC (ADCON1<7:5>) is not equal to ‘111’
B1
B1
B2
B2
© 2010 Microchip Technology Inc.