ST7FLITE09M6TR STMicroelectronics, ST7FLITE09M6TR Datasheet - Page 80

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ST7FLITE09M6TR

Manufacturer Part Number
ST7FLITE09M6TR
Description
IC MCU 8BIT FLASH 16SOIC
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST7FLITE09M6TR

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI
Peripherals
PWM, WDT
Number Of I /o
13
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-SOIC
Processor Series
ST7FLITE0x
Core
ST7
Data Bus Width
8 bit
Development Tools By Supplier
ST7FLIT0-IND/USB, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
For Use With
497-5858 - EVAL BOARD PLAYBACK ST7FLITE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ST7FLITE09M6TR
Manufacturer:
ST
0
ST7LITE0xY0, ST7LITESxY0
INSTRUCTION GROUPS (cont’d)
80/124
1
JRULE
LD
MUL
NEG
NOP
OR
POP
PUSH
RCF
RET
RIM
RLC
RRC
RSP
SBC
SCF
SIM
SLA
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
XOR
Mnemo
Jump if (C + Z = 1)
Load
Multiply
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
Disable Interrupts
Shift left Arithmetic
Shift left Logic
Shift right Logic
Shift right Arithmetic
Subtraction
SWAP nibbles
Test for Neg & Zero
S/W trap
Wait for Interrupt
Exclusive OR
Description
Unsigned <=
dst <= src
X,A = X * A
neg $10
A = A + M
pop reg
pop CC
push Y
C = 0
I = 0
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
I = 1
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
S/W interrupt
A = A XOR M
Function/Example
reg, M
A, X, Y
reg, M
reg, M
A
reg
CC
M
reg, M
reg, M
A
reg, M
reg, M
reg, M
A
A
Dst
M, reg
X, Y, A
M
M
M
reg, CC
M
M
M
Src
H
H
0
0
1
1
0
I
I
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
C
C
C
C
C
C
0
0
1

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