Z8F2422VS020SG Zilog, Z8F2422VS020SG Datasheet - Page 80

• Manufacturer Part Number: Z8F2422VS020SG
• Description: IC ENCORE MCU FLASH 24K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2422VS020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z8F242x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F64200100KITG, ZENETSC0100ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4253; Z8F2422VS020SG

PS019921-0308
Interrupt Vectors and Priority
Interrupt Assertion
Caution:
Software Interrupt Assertion
Caution:
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all of
the interrupts were enabled with identical interrupt priority (all as Level 2 interrupts, for
example), then interrupt priority would be assigned from highest to lowest as specified in
Table 23
which, in turn, always have higher priority than Level 1 interrupts. Within each interrupt
priority level (Level 1, Level 2, or Level 3), priority is assigned as specified in
page 63. Reset, Watchdog Timer interrupt (if enabled), and Illegal Instruction Trap always
have highest priority.
Interrupt sources assert their interrupt requests for only a single system clock period
(single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the
corresponding bit in the Interrupt Request register is cleared until the next interrupt
occurs. Writing a 0 to the corresponding bit in the Interrupt Request register likewise
clears the interrupt request.
Program code can generate interrupts directly. Writing a 1 to the desired bit in the Interrupt
Request register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is
automatically cleared to 0.
The following style of coding to clear bits in the Interrupt Request registers is
NOT recommended. All incoming interrupts that are received between
execution of the first LDX command and the last LDX command are lost.
the Interrupt Request 0 register is recommended:
The following style of coding to generate software interrupts by setting bits in
the Interrupt Request registers is NOT recommended. All incoming interrupts
To avoid missing interrupts, the following style of coding to clear bits in
on page 63. Level 3 interrupts always have higher priority than Level 2 interrupts
Poor coding style that can result in lost interrupt requests:
Good coding style that avoids lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
ANDX IRQ0, MASK
Z8 Encore! XP
Product Specification
®
Interrupt Controller
F64XX Series
Table 23
on
66