Z8F0822PJ020EG Zilog, Z8F0822PJ020EG Datasheet - Page 138

• Manufacturer Part Number: Z8F0822PJ020EG
• Description: IC ENCORE MCU FLASH 8K 28DIP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0822PJ020EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Processor Series: Z8F082xx
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 19
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 5 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4207; Z8F0822PJ020EG

Table 67. SPI Diagnostic State Register (SPIDST)
Table 68. SPI Baud Rate High Byte Register (SPIBRH)
PS022517-0508
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
SPI Diagnostic State Register
SPI Baud Rate High and Low Byte Registers
SCKEN
7
7
1 = SS pin driven High (1).
This bit has no effect if SSIO = 0 or SPI configured as a Slave
The SPI Diagnostic State Register provides observability of internal state. This is a read
only register used for SPI diagnostics.
SCKEN–Shift Clock Enable
0 = The internal Shift Clock Enable signal is deasserted
1 = The internal Shift Clock Enable signal is asserted (shift register is updates on
TCKEN–Transmit Clock Enable
0 = The internal Transmit Clock Enable signal is deasserted.
1 = The internal Transmit Clock Enable signal is asserted. When this is asserted the serial
data out is updated on the next system clock (MOSI or MISO).
SPISTATE–SPI State Machine
Defines the current state of the internal SPI State Machine.
The SPI Baud Rate High and Low Byte Registers combine to form a 16-bit reload value,
BRG[15:0], for the SPI Baud Rate Generator. When configured as a general purpose
timer, the interrupt interval is calculated using the following equation:
Interrupt Interval (s) = System Clock Period (s) × BRG[15:0]
next system clock)
TCKEN
6
6
5
5
4
4
F64H
F66H
BRH
R/W
R
0
1
3
3
SPISTATE
Z8 Encore! XP
2
2
Product Specification
Serial Peripheral Interface
1
1
®
F0822 Series
0
0
125