W77E058A40PL Nuvoton Technology Corporation of America, W77E058A40PL Datasheet - Page 22

• Manufacturer Part Number: W77E058A40PL
• Description: IC MCU 8-BIT 32K FLASH 44-PLCC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: W77r

Specifications of W77E058A40PL

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, Serial Port
• Peripherals: POR, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• Cpu Family: W77
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 40MHz
• Interface Type: UART
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

REN_1: Receive enable: When set to 1 serial reception is enabled, otherwise reception is disabled.
TB8_1: This is the 9th bit to be transmitted in modes 2 and 3. This bit is set and cleared by software
RB8_1: In modes 2 and 3 this is the received 9th data bit. In mode 1, if SM2_1 = 0, RB8_1 is the stop
TI_1:
RI_1:
Serial Data Buffer 1
SBUF1.7-0: Serial data of the serial port 1 is read from or written to this location. It actually consists of
ROMMAP
WS:
Bit:
become divide by 4 of the oscillator clock. This results in faster synchronous serial
communication.
as desired.
bit that was received. In mode 0 it has no function.
Transmit interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
at the beginning of the stop bit in all other modes during serial transmission. This bit must be
cleared by software.
Receive interrupt flag: This flag is set by hardware at the end of the 8th bit time in mode 0, or
halfway through the stop bits time in the other modes during serial reception. However the
restrictions of SM2_1 apply to this bit. This bit can be cleared only by software.
Wait State Signal Enable. Setting this bit enables the WAIT signal on P4.0. The device will
sample the wait state control signal WAIT via P4.0 during MOVX instruction. This bit is time
access protected.
ROMMAP
CKCON
ANL
MOV
MOV
ORL
TA
two separate 8-bit registers. One is the receive resister, and the other is the transmit
buffer. Any read access gets data from the receive data buffer, while write accesses are
to the transmit data buffer.
SBUF1.7 SBUF1.6 SBUF1.5 SBUF1.4 SBUF1.3 SBUF1.2 SBUF1.1 SBUF1.0
Mnemonic: SBUF1
Mnemonic: ROMMAP
REG
Bit:
7
C7H
REG
REG
CKCON,#11111000B
TA,#AAH
TA,#55H
ROMMAP,#10000000B ; Set WS bit and stretch value = 0 to enable wait
signal.
WS
7
6
C2H
8EH
6
1
5
5
-
; Set stretch value=0
- 22 -
4
4
-
3
3
-
Address: C1h
Address: C2h
2
2
1
W77E058A
1
1
1
0
0
0