Z86E4412VSG Zilog, Z86E4412VSG Datasheet - Page 46

• Manufacturer Part Number: Z86E4412VSG
• Description: IC MICROCONTROLLER 16K 44-PLCC
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E4412VSG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: EBI/EMI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-LCC (J-Lead)
• Processor Series: Z86E4xx
• Core: Z8
• Data Bus Width: 8 bit
• Data Ram Size: 237 B
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 3.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z86E4400ZDV, Z86E4400ZDP, Z86E4400ZDF, Z86E3400ZDV, Z86E3400ZDS, Z86E3400ZDP, Z86C4001ZDV
• Minimum Operating Temperature: 0 C
• For Use With: 309-1042 - ADAPTER 44-PLCC ZIF TO 44-PLCC309-1041 - ADAPTER 44-PLCC TO 44-PLCC309-1038 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1037 - ADAPTER 44-PLCC TO 40-DIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3981; Z86E4412VSG

FUNCTIONAL DESCRIPTION (Continued)
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Stop-Mode Recovery Delay Select (D5). The 5 ms RE-
SET delay after Stop-Mode Recovery is disabled by pro-
gramming this bit to a zero. A "1" in this bit will cause a 5
ms RESET delay after Stop-Mode Recovery. The default
condition of this bit is 1. If the fast wake up mode is select-
ed, the Stop-Mode Recovery source needs to be kept ac-
tive for at least 5TpC.
Stop-Mode Recovery Level Select (D6). A "1" in this bit
defines that a high level on any one of the recovery sourc-
es wakes the MCU from STOP Mode. A 0 defines low level
recovery. The default value is 0.
Cold or Warm Start (D7). This bit is set by the device
upon entering STOP Mode. A "0" in this bit indicates that
the device has been reset by POR (cold). A "1" in this bit
indicates the device was awakened by a SMR source
(warm).
Stop-Mode Recovery Register 2 (SMR2). This register
contains additional Stop-Mode Recovery sources. When
the Stop-Mode Recovery sources are selected in this reg-
ister then SMR Register Bits D2, D3, and D4 must be 0.
0
0
1
46
D1
D4
SMR:10
0
0
0
0
1
1
1
1
0
1
0
Table 12. Stop-Mode Recovery Source
D0
D3
0
0
1
1
0
0
1
1
POR and/or external reset recovery
Logical AND of P20 through P23
Logical AND of P20 through P27
D2
0
1
0
1
0
1
0
1
Description of Action
POR recovery only
P30 transition
P31 transition (Not in analog
mode)
P32 transition (Not in analog
mode)
P33 transition (Not in analog
mode)
P27 transition
Logical NOR of Port 2 bits 0-3
Logical NOR of Port 2 bits 0-7
SMR Source selection
Operation
P R E L I M I N A R Y
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT is disabled after Pow-
er-On Reset and initially enabled by executing the WDT in-
struction and refreshed on subsequent executions of the
WDT instruction. The WDT is driven either by an on-board
RC oscillator or an external oscillator from XTAL1 pin. The
POR clock source is selected with bit 4 of the WDT regis-
ter.
Note: Execution of the WDT instruction affects the Z (Ze-
ro), S (Sign), and V (Overflow) flags.
WDT Time-Out Period (D0 and D1). Bits 0 and 1 control
a tap circuit that determines the time-out periods that can
be obtained (Table 13). The default value of D0 and D1
are 1 and 0, respectively.
Notes:
WDT During HALT Mode (D2). This bit determines
whether or not the WDT is active during HALT Mode. A "1"
indicates that the WDT is active during HALT. A "0" dis-
ables the WDT in HALT Mode. The default value is "1".
WDT During STOP Mode (D3). This bit determines
whether or not the WDT is active during STOP mode. A "1"
indicates active during STOP. A "0" disables the WDT dur-
ing STOP Mode. This is applicable only when the WDT
clock source is the internal RC oscillator.
Clock Source For WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscil-
lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1, and the WDT is
stopped in STOP Mode. The default configuration of this
bit is 0, which selects the RC oscillator.
*The default setting is 10 ms.
D1
0
0
1
1
Table 13. Time-out Period of WDT
D0
0
1
0
1
Time-out of
the Internal
RC OSC
10 ms*
20 ms
80 ms
5 ms
DS97Z8X1500
Time-out of
the System
2048 SCLK
256 SCLK*
128 SCLK
512 SCLK
Clock
Zilog