STM32F105VCT7 STMicroelectronics, STM32F105VCT7 Datasheet - Page 66

• Manufacturer Part Number: STM32F105VCT7
• Description: MCU 32BIT ARM 256K FLASH 100-LQF
• Manufacturer: STMicroelectronics
• Series: STM32r

Specifications of STM32F105VCT7

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 72MHz
• Connectivity: CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 80
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Processor Series: STM32F105x
• Core: ARM Cortex M3
• Data Bus Width: 32 bit
• Data Ram Size: 64 KB
• Interface Type: CAN, I2C, SPI, USART
• Maximum Clock Frequency: 72 MHz
• Number Of Programmable I/os: 80
• Number Of Timers: 10
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• On-chip Dac: 12 bit, 2 Channel
• Featured Product: STM32 Cortex-M3 Companion Products
• Eeprom Size: -
• For Use With: 497-10591 - DAUGHTER BOARD FOR STM32497-9040 - DEV KIT FOR STM32497-9041 - DEV KIT FOR STM32497-9042 - DEV KIT FOR STM32497-9043 - DEV KIT FOR STM32497-8924 - EVAL BOARD FOR STM32F107VCT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
Table 43.
1. Based on design simulation and/or characterization results, not tested in production.
66/101
f
1/t
t
t
t
t
t
t
t
t
DuCy(SCK)
t
t
t
t
t
t
t
t
CK
r(CK)
f(CK)
w(CKH)
w(CKL)
v(WS)
h(WS)
su(WS)
h(WS)
su(SD_MR)
su(SD_SR)
h(SD_MR)
h(SD_SR)
v(SD_ST)
h(SD_ST)
v(SD_MT)
h(SD_MT)
c(CK)
Symbol
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)(3)
(1)
(1)
(1)
(1)
(1)
(1)
I
2
S characteristics
I
I
I
I
WS valid time
WS hold time
WS setup time
WS hold time
I2S slave input clock duty
cycle
Data input setup time
Data input hold time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
2
2
2
2
S clock frequency
S clock rise and fall time
S clock high time
S clock low time
Parameter
Master data: 16 bits, audio
freq = 48 K
Slave
capacitive load C
Master f
audio freq = 48 K
Master mode
Master mode
Slave mode
Slave mode
Slave mode
Master receiver
Slave receiver
Master receiver
Slave receiver
Slave transmitter
(after enable edge)
Slave transmitter
(after enable edge)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
Doc ID 15274 Rev 5
Conditions
PCLK
= 16 MHz,
L
= 50 pF
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
I2S2
I2S3
1.52
Min
333
317
30
10
23
33
29
27
11
0
3
0
0
4
9
0
8
3
8
2
4
2
4
4
STM32F105xx, STM32F107xx
Max
1.54
320
336
6.5
70
8
5
2
MHz
Unit
ns
ns
%