S9S08SG4E2MTG Freescale Semiconductor, S9S08SG4E2MTG Datasheet - Page 149
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S9S08SG4E2MTG
Manufacturer Part Number
S9S08SG4E2MTG
Description
MCU 4K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG4E2MTG
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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10.1.4.4
In FLL bypassed internal low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the internal reference clock. The BDC clock is not available.
10.1.4.5
In FLL bypassed external mode, the FLL is enabled and controlled by an external reference clock, but is
bypassed. The ICS supplies a clock derived from the external reference clock. The external reference clock
can be an external crystal/resonator supplied by an OSC controlled by the ICS, or it can be another external
clock source. The BDC clock is supplied from the FLL.
10.1.4.6
In FLL bypassed external low power mode, the FLL is disabled and bypassed, and the ICS supplies a clock
derived from the external reference clock. The external reference clock can be an external crystal/resonator
supplied by an OSC controlled by the ICS, or it can be another external clock source. The BDC clock is
not available.
10.1.4.7
In stop mode the FLL is disabled and the internal or external reference clocks can be selected to be enabled
or disabled. The BDC clock is not available and the ICS does not provide an MCU clock source.
10.2
There are no ICS signals that connect off chip.
10.3
Figure 10-1
Freescale Semiconductor
ICSTRM
ICSSC
ICSC1
ICSC2
Name
External Signal Description
Register Definition
is a summary of ICS registers.
FLL Bypassed Interna
FLL Bypassed Externa
FLL Bypassed Externa
Stop (STOP)
W
W
W
W
R
R
R
R
0
7
CLKS
BDIV
MC9S08SG8 MCU Series Data Sheet, Rev. 6
0
6
Table 10-1. ICS Register Summary
RANGE
0
5
l Low Power (FBILP)
l (FBE)
l Low Power (FBELP)
IREFST
RDIV
HGO
4
TRIM
LP
3
CLKST
Chapter 10 Internal Clock Source (S08ICSV2)
EREFS
IREFS
2
ERCLKEN
IRCLKEN
OSCINIT
1
EREFSTEN
IREFSTEN
FTRIM
0
149
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