S9S08SG4E2MTG Freescale Semiconductor, S9S08SG4E2MTG Datasheet - Page 153
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S9S08SG4E2MTG
Manufacturer Part Number
S9S08SG4E2MTG
Description
MCU 4K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG4E2MTG
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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10.4
10.4.1
The seven states of the ICS are shown as a state diagram and are described below. The arrows indicate the
allowed movements between the states.
10.4.1.1
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
conditions occur:
Freescale Semiconductor
FLL Bypassed
External Low
Power(FBELP)
Field
IREFS=0
CLKS=10
BDM Disabled
and LP=1
1
0
Functional Description
Operational Modes
OSC Initialization — If the external reference clock is selected by ERCLKEN or by the ICS being in FEE, FBE,
or FBELP mode, and if EREFS is set, then this bit is set after the initialization cycles of the external oscillator
clock have completed. This bit is only cleared when either ERCLKEN or EREFS are cleared.
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
FLL Engaged Internal (FEI)
Entered from any state
when MCU enters stop
Table 10-5. ICS Status and Control Register Field Descriptions (continued)
IREFS=0
CLKS=10
BDM Enabled
or LP =0
FLL Bypassed
External (FBE)
MC9S08SG8 MCU Series Data Sheet, Rev. 6
Figure 10-7. Clock Switching Modes
FLL Engaged
External (FEE)
FLL Engaged
Internal (FEI)
IREFS=1
CLKS=00
IREFS=0
CLKS=00
Stop
Description
Chapter 10 Internal Clock Source (S08ICSV2)
FLL Bypassed
Internal (FBI)
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
IREFS=1
CLKS=01
BDM Enabled
or LP=0
FLL Bypassed
Internal Low
Power(FBILP)
IREFS=1
CLKS=01
BDM Disabled
and LP=1
153
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