S9S08SG8E2CTJ Freescale Semiconductor, S9S08SG8E2CTJ Datasheet - Page 15
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S9S08SG8E2CTJ
Manufacturer Part Number
S9S08SG8E2CTJ
Description
MCU 2K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG8E2CTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S08SG8E2CTJ
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
S9S08SG8E2CTJR
Manufacturer:
SAMSUNG
Quantity:
400 000
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Section Number
13.5 Initialization/Application Information ..........................................................................................196
14.1 Introduction ...................................................................................................................................199
14.2 Register Definition ........................................................................................................................204
14.3 Functional Description ..................................................................................................................211
15.1 Introduction ...................................................................................................................................219
15.2 External Signal Description ..........................................................................................................224
15.3 Modes of Operation .......................................................................................................................225
15.4 Register Definition ........................................................................................................................225
Freescale Semiconductor
13.4.1 RTC Operation Example .................................................................................................195
14.1.1 Features ...........................................................................................................................201
14.1.2 Modes of Operation ........................................................................................................201
14.1.3 Block Diagram ................................................................................................................202
14.2.1 SCI Baud Rate Registers (SCIBDH, SCIBDL) ..............................................................204
14.2.2 SCI Control Register 1 (SCIC1) .....................................................................................205
14.2.3 SCI Control Register 2 (SCIC2) .....................................................................................206
14.2.4 SCI Status Register 1 (SCIS1) ........................................................................................207
14.2.5 SCI Status Register 2 (SCIS2) ........................................................................................209
14.2.6 SCI Control Register 3 (SCIC3) .....................................................................................210
14.2.7 SCI Data Register (SCID) ...............................................................................................211
14.3.1 Baud Rate Generation .....................................................................................................211
14.3.2 Transmitter Functional Description ................................................................................212
14.3.3 Receiver Functional Description .....................................................................................213
14.3.4 Interrupts and Status Flags ..............................................................................................215
14.3.5 Additional SCI Functions ...............................................................................................216
15.1.1 Features ...........................................................................................................................221
15.1.2 Block Diagrams ..............................................................................................................221
15.1.3 SPI Baud Rate Generation ..............................................................................................223
15.2.1 SPSCK — SPI Serial Clock ............................................................................................224
15.2.2 MOSI — Master Data Out, Slave Data In ......................................................................224
15.2.3 MISO — Master Data In, Slave Data Out ......................................................................224
15.2.4 SS — Slave Select ...........................................................................................................224
15.3.1 SPI in Stop Modes ..........................................................................................................225
15.4.1 SPI Control Register 1 (SPIC1) ......................................................................................225
15.4.2 SPI Control Register 2 (SPIC2) ......................................................................................226
15.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................227
15.4.4 SPI Status Register (SPIS) ..............................................................................................228
Serial Communications Interface (S08SCIV4)
Serial Peripheral Interface (S08SPIV3)
MC9S08SG8 MCU Series Data Sheet, Rev. 6
Chapter 14
Chapter 15
Title
Page
15
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