S9S08SG8E2CTJ Freescale Semiconductor, S9S08SG8E2CTJ Datasheet - Page 68
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S9S08SG8E2CTJ
Manufacturer Part Number
S9S08SG8E2CTJ
Description
MCU 2K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG8E2CTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S9S08SG8E2CTJ
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
S9S08SG8E2CTJR
Manufacturer:
SAMSUNG
Quantity:
400 000
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1
Chapter 5 Resets, Interrupts, and General System Control
5.7.3
This high page register is a write-once register so only the first write after reset is honored. It can be read
at any time. Any subsequent attempt to write to SOPT1 (intentionally or unintentionally) is ignored to
avoid accidental changes to these sensitive settings. SOPT1 should be written during the user’s reset
initialization program to set the desired controls even if the desired settings are the same as the reset
settings.
67
NOTE: Bit 4 is reserved. Writes change the value, but have no effect on this MCU.
COPT[1:0]
Reset:
STOPE
IICPS
Field
7:6
5
2
W
R
System Options Register 1 (SOPT1)
COP Watchdog Timeout — These write-once bits select the timeout period of the COP. COPT along with
COPCLKS in SOPT2 defines the COP timeout period. See
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
IIC Pin Select — This bit selects the location of the SDA and SCL pins of the IIC module.
0 SDA on PTA2, SCL on PTA3.
1 SDA on PTB6, SCL on PTB7.
1
7
COPT
= Unimplemented or Reserved
1
6
Figure 5-4. System Options Register 1 (SOPT1)
Table 5-5. SOPT1 Register Field Descriptions
MC9S08SG8 MCU Series Data Sheet, Rev. 6
STOPE
0
5
4
0
1
Description
Table
3
0
0
5-1.
IICPS
0
2
Freescale Semiconductor
0
0
1
0
0
0
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