S9S08SG4E2MTJ Freescale Semiconductor, S9S08SG4E2MTJ Datasheet - Page 59
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S9S08SG4E2MTJ
Manufacturer Part Number
S9S08SG4E2MTJ
Description
MCU 4K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG4E2MTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 5
Resets, Interrupts, and General System Control
5.1
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt
in the MC9S08SG8 Series. Some interrupt sources from peripheral modules are discussed in greater detail
within other sections of this data sheet. This section gathers basic information about all reset and interrupt
sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog are not part of on-chip peripheral systems with their own chapters.
5.2
Reset and interrupt features include:
5.3
Resetting the MCU provides a way to start processing from a known set of initial conditions. During reset,
most control and status registers are forced to initial values and the program counter is loaded from the
reset vector (0xFFFE:0xFFFF). On-chip peripheral modules are disabled and I/O pins are initially
configured as general-purpose high-impedance inputs with pull-up devices disabled. The I bit in the
condition code register (CCR) is set to block maskable interrupts so the user program has a chance to
initialize the stack pointer (SP) and system control settings. SP is forced to 0x00FF at reset.
The MC9S08SG8 Series has the following sources for reset:
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register (SRS).
Freescale Semiconductor
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Multiple sources of reset for flexible system configuration and reliable operation
Reset status register (SRS) to indicate source of most recent reset
Separate interrupt vector for each module (reduces polling overhead) (see
Power-on reset (POR)
External pin reset (PIN)
Low-voltage detect (LVD)
Computer operating properly (COP) timer
Illegal opcode detect (ILOP)
Illegal address detect (ILAD)
Background debug forced reset
Introduction
Features
MCU Reset
MC9S08SG8 MCU Series Data Sheet, Rev. 6
Table
5-2)
58
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