MCHC908QT2MDWER Freescale Semiconductor, MCHC908QT2MDWER Datasheet - Page 136
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MCHC908QT2MDWER
Manufacturer Part Number
MCHC908QT2MDWER
Description
IC MCU 1.5K FLASH W/ADC 8-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QY4MDWER.pdf
(184 pages)
Specifications of MCHC908QT2MDWER
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
5
Program Memory Size
1.5KB (1.5K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Processor Series
HC08QT
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
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Development Support
15.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable and status bits.
BRKE — Break Enable Bit
BRKA — Break Active Bit
15.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint
address. Reset clears the break address registers.
136
This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to
bit 7. Reset clears the BRKE bit.
This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA
generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset
clears the BRKA bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
1 = Break address match
0 = No break address match
Address: $FE0B
Address: $FE09
Address: $FE0A
Reset:
Read:
Write:
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 15-3. Break Status and Control Register (BRKSCR)
BRKE
Bit 7
Bit 15
Bit 7
Bit 7
Bit 7
0
0
0
Figure 15-4. Break Address Register High (BRKH)
Figure 15-5. Break Address Register Low (BRKL)
= Unimplemented
BRKA
Bit 14
MC68HC908QY/QT Family Data Sheet, Rev. 6
Bit 6
6
0
6
0
6
0
Bit 13
Bit 5
5
0
0
5
0
5
0
Bit 12
Bit 4
4
0
0
4
0
4
0
Bit 11
Bit 3
3
0
0
3
0
3
0
Bit 10
Bit 2
2
0
0
2
0
2
0
Bit 9
Bit 1
1
0
0
1
0
1
0
Freescale Semiconductor
Bit 0
Bit 0
Bit 8
Bit 0
Bit 0
0
0
0
0
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