MC908QY4AMDWE Freescale Semiconductor, MC908QY4AMDWE Datasheet - Page 122
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MC908QY4AMDWE
Manufacturer Part Number
MC908QY4AMDWE
Description
IC MCU 8BIT 4K FLASH 16-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908QT1ACDWE.pdf
(200 pages)
Specifications of MC908QY4AMDWE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM
Number Of I /o
13
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-SOIC (0.300", 7.5mm Width)
Processor Series
HC08QY
Core
HC08
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
13
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, M68CBL05AE, DEMO908QB8, DEMO908QC16
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 6 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
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System Integration Module (SIM)
The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop
recovery. It is then used to time the recovery period.
Figure 13-18
13.8 SIM Registers
The SIM has two memory mapped registers.
13.8.1 SIM Reset Status Register
The SRSR register contains flags that show the source of the last reset. The status register will
automatically clear after reading SRSR. A power-on reset sets the POR bit and clears all other bits in the
register. All other reset sources set the individual flag bits but do not clear the register. More than one
reset source can be flagged at any time depending on the conditions at the time of the internal or external
reset. For example, the POR and LVI bit can both be set if the power supply has a slow rise time.
122
ADDRESS BUS
INTERRUPT
BUSCLKX4
ADDRESS BUS
NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
shows the stop mode recovery time from interrupt or break
Read:
Write:
POR:
To minimize stop current, all pins configured as inputs should be driven to
a logic 1 or logic 0.
DATA BUS
CPUSTOP
R/W
POR
Bit 7
1
Figure 13-18. Stop Mode Recovery from Interrupt
Figure 13-19. SIM Reset Status Register (SRSR)
STOP ADDR
= Unimplemented
PIN
MC68HC908QYA/QTA Family Data Sheet, Rev. 3
STOP +1
Figure 13-17. Stop Mode Entry Timing
6
0
PREVIOUS DATA
COP
5
0
STOP ADDR + 1
STOP + 2
ILOP
NOTE
STOP RECOVERY PERIOD
4
0
NEXT OPCODE
Figure 13-17
STOP + 2
ILAD
3
0
SAME
MODRST
shows stop mode entry timing and
SP
2
0
SAME
SP – 1
LVI
SAME
1
0
SAME
Freescale Semiconductor
SP – 2
Bit 0
0
0
SP – 3
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