MC9S08SH16CTGR Freescale Semiconductor, MC9S08SH16CTGR Datasheet - Page 78
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MC9S08SH16CTGR
Manufacturer Part Number
MC9S08SH16CTGR
Description
MCU 8BIT 16K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08SH16CTG.pdf
(328 pages)
Specifications of MC9S08SH16CTGR
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-TSSOP
Package
16TSSOP
Family Name
HCS08
Maximum Speed
40 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
13
Interface Type
SCI/SPI
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Chapter 6 Parallel Input/Output Control
6.4
Port A[3:0] and port B[3:0] pins can be configured as external interrupt inputs and as an external means of
waking the MCU from stop3 or wait low-power modes.
The block diagram for the pin interrupts is shown
Writing to the PTxPSn bits in the port interrupt pin enable register (PTxPS) independently enables or
disables each port pin interrupt. Each port can be configured as edge sensitive or edge and level sensitive
based on the PTxMOD bit in the port interrupt status and control register (PTxSC). Edge sensitivity can
be software programmed to be either falling or rising; the level can be either low or high. The polarity of
the edge or edge and level sensitivity is selected using the PTxESn bits in the port interrupt edge select
register (PTxES).
Synchronous logic is used to detect edges. Prior to detecting an edge, enabled pin interrupt inputs must be
at the deasserted logic level. A falling edge is detected when an enabled port input signal is seen as a logic
1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle.
A rising edge is detected when the input signal is seen as a logic 0 during one bus cycle and then a logic 1
during the next cycle.
6.4.1
A valid edge on an enabled pin interrupt sets PTxIF in PTxSC. If PTxIE in PTxSC is set, an interrupt
request is presented to the CPU. To clear PTxIF, write a 1 to PTxACK in PTxSC.
78
PIxn
PIxn
PTxESn
PTxES0
Pin Interrupts
0
0
1
1
S
S
Edge-Only Sensitivity
If a pin is enabled for interrupt on edge-sensitive only, a falling (or rising)
edge on the pin does not latch an interrupt request if another pin interrupt is
already asserted.
To prevent losing an interrupt request on one pin because another pin is
asserted, software can disable the asserted pin interrupt while having the
unasserted pin interrupt enabled. The asserted status of a pin is reflected by
its associated I/O general purpose data register.
PTxPSn
PTxPS0
Figure 6-2. Pin Interrupt Block Diagram
MC9S08SH32 Series Data Sheet, Rev. 2
PTxMOD
PRELIMINARY
V
DD
NOTE
D
Figure
CK
CLR
Q
6-2.
INTERRUPT FF
PORT
PTxACK
RESET
STOP
SYNCHRONIZER
STOP BYPASS
BUSCLK
PTxIE
Freescale Semiconductor
PTxIF
PTx
INTERRUPT
REQUEST
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