C8051T617-GM Silicon Laboratories Inc, C8051T617-GM Datasheet - Page 115
![IC 8051 MCU 16K BYTE-PROG 24-QFN](/photos/12/15/121587/c8051f9xx_24-qfn_sml.jpg)
C8051T617-GM
Manufacturer Part Number
C8051T617-GM
Description
IC 8051 MCU 16K BYTE-PROG 24-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T61xr
Specifications of C8051T617-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
24-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
336-1438-5
- Current page: 115 of 218
- Download datasheet (2Mb)
21.1.3. Interfacing Port I/O to 5V Logic
All Port I/O configured for digital, open-drain operation are capable of interfacing to digital logic operating at
a supply voltage higher than VDD and less than 5.25 V. An external pullup resistor to the higher supply
voltage on output pins is typically required for most systems.
Important Notes: The absolute maximum voltage of any Port I/O pin should be limited to VDD + 3.6V.
When interfacing to systems with supply voltages higher than 3.6V, care must be taken to limit the voltage
on I/O pins when the VDD supply to the device is not present. In a multi-voltage interface, the external pul-
lup resistor should be sized to allow a current of at least 150 µA to flow into the Port pin when the supply
voltage is between (VDD + 0.6 V) and (VDD + 1.0 V). Once the Port pin voltage increases beyond this
range, the current flowing into the Port pin is minimal.
WEAKPUD
(Weak Pull-Up Disable)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
XBARE
(Crossbar
Enable)
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
To/From Analog
Peripheral
PxMDIN.x
(1 for digital)
(0 for analog)
Figure 21.2. Port I/O Cell Block Diagram
Rev 1.0
C8051T610/1/2/3/4/5/6/7
VDD
GND
VDD
(WEAK)
PORT
PAD
115
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