C8051T617-GM Silicon Laboratories Inc, C8051T617-GM Datasheet - Page 136
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C8051T617-GM
Manufacturer Part Number
C8051T617-GM
Description
IC 8051 MCU 16K BYTE-PROG 24-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T61xr
Specifications of C8051T617-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
21
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
24-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
336-1438-5
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C8051T610/1/2/3/4/5/6/7
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 22.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “25. Timers” on page 170.
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 22.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 22.2.
Figure 22.4 shows the typical SCL generation described by Equation 22.2. Notice that T
twice as large as T
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 22.1.
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
136
Timer Source
Overflows
SCL
LOW
Equation 22.1. Minimum SCL High and Low Times
T
Low
. The actual SCL output may vary due to other devices on the bus (SCL may be
Figure 22.4. Typical SMBus SCL Generation
Table 22.1. SMBus Clock Source Selection
SMBCS1
T
Equation 22.2. Typical SMBus Bit Rate
HighMin
0
0
1
1
BitRate
T
SMBCS0
=
High
T
0
1
0
1
LowMin
=
f
--------------------------------------------- -
ClockSourceOverflow
Rev 1.0
=
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
SMBus Clock Source
--------------------------------------------- -
f
ClockSourceOverflow
Timer 0 Overflow
Timer 1 Overflow
3
1
SCL High Timeout
HIGH
is typically
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